Capitalizing on the Architectural Flexibility of FPGAs with RISC-V and a Simplified Programming Flow

By Efinix, Inc.
EETimes (April 26, 2022)

Microprocessors have traditionally dominated the realm of computing, and in this drive toward more compute capabilities, silicon-based ICs were consistently improved upon in device density. Every couple of years, the transistor density doubled in accordance with Moore’s Law, leading to a veritable goldmine of technological innovation. Amid this “gold rush,” several large semiconductor companies created a foothold in the market that has been unshakeable given the expertise and expense of creating custom silicon. Now, with the ever-increasing demand for compute-hungry devices, ASICs, FPGAs, and embedded processors alike are being asked to perform more complex tasks. The barriers to entry have been far too high.

On the end-application side of the spectrum, the implementation of a system depends heavily on the bottom line. The cost of the IC, licensing fees, and ease of programmability all directly contribute to the price to create modern electronics. Designers and developers alike have relied on both accelerator ASICs and traditional embedded processor solutions in application-specific standard products (ASSPs) to achieve the core functionality of their design while also benefiting from the well-understood design flow of generic processors. The goal: a rapid time to market (TTM) with minimal cost while meeting the growing compute complexities demanded in modern applications. The question then becomes: Which chipset(s) is best able to run the application most efficiently with the least development time and cost?

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