JTAG IEEE 1149.1 Standard WG

Official IEEE Std. 1149.1 Standard Working Group

Scope

The IEEE 1149.1 standard defines test logic that can be included in an integrated circuit to provide standardized approaches to
- testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or other substrate;
- testing the integrated circuit itself; and
- observing or modifying circuit activity during the component's normal operation.
The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).

Purpose This subclause provides a general overview of the operation of a component compatible with this standard and provides a background to the detailed discussion in later subclauses. The circuitry defined by this standard allows test instructions and associated test data to be fed into a component and, subsequently, allows the results of execution of such instructions to be read out. All information (instructions, test data, and test results) is communicated in a serial format. The sequence of operations would be controlled by a bus master, which could be either an automatic test equipment (ATE) or a component that interfaces to a higher-level test bus as a part of a complete system maintenance architecture. Control is achieved through signals applied to the Test Mode Select (TMS) and Test Clock (TCK) inputs of the various components connected to the bus master. Starting from an initial state in which the test circuitry defined by this standard is inactive, a typical sequence of operations would be as follows.The first steps would be, in general, to load serially into the component the instruction binary code for the particular operation to be performed. The test logic defined by this standard is designed such that the serial movement of instruction information is not apparent to those circuit blocks whose operation is controlled by the instruction.		IC with support for 1149.1-2013
The instruction applied to these blocks changes only on completion of the shifting (instruction load) process. Once the instruction has been loaded, the selected test circuitry is configured to respond. In some cases, however, it is necessary to load data into the selected test circuitry before a meaningful response can be made. Such data is loaded into the component serially in a manner analogous to the process used previously to load the instruction. Note that the movement of test data has no effect on the instruction present in the test circuitry. After execution of the test instruction, based where necessary on supplied data, the results of the test can be examined by shifting data out of the component to or through the bus master. Note that in cases where the same test operation is to be repeated but with different data, new test data can be shifted into the component while the test results are shifted out. There is no need for the instruction to be reloaded. Operation of the test circuitry may proceed by loading and executing several further instructions in a manner similar to that described and would conclude by returning the test circuitry and, where required, on-chip system circuitry to its initial state.
*Changes proposed for P1149.1-2013* (Examples of new BSDL attributes and PDL are in the discussion area below)

*Officers*
*Chair* CJ Clark Intellitech	*Vice Chair* Carol Pyron Freescale	*Secretary* Bill Tuthill Raytheon	*Editor* Carl Barnhart SiliconAid	*Friday Secretary* Roland Latvala Freescale