Eliminate Waste, Share IP, Raise Profitability, says eSilicon.

The economics of chip-making could be positively transformed if companies share non-core IP, says Jack Harding, CEO of eSilion.”Non-differentiated IP should be put into the public domain for free to see what good things come out of that,” Harding told IEF2013 in Dublin.

“If we and other companies can share non-core technology we can raise the level for everyone with a bit more co-operation,” said Harding, “there are a series of products we are displaying on-line for free. Out of that we hope to generate some goodwill, improve our presence in the market, improve profits and generate growth.”

The problem Harding is addressing is the slowing down of the ASIC industry. “It costs $200 million to design and scale an IC at 20nm,” said Harding, “but there’s a 14% drop in design starts expected between 2011 and 16. There’s a dearth of start-ups in semiconductors. Risk capital has dried up. This plan might lower the barriers for new companies.”

“Complexity is increasing; design starts are decreasing,” said Harding, “people are moving away from building hardware all the time. There’s an opportunity to re-aggregate the supply chain and purge out waste.”

There’s massive waste with every SOC,” said Harding, “the wrong process is used with the wrong library. There are dozens of variables you can optimise.”

“If we can get the waste out we can improve the industry’s bottom line,” says Harding, “We can remove waste, redundancy and inefficiency, and reduce cost, risk and time-to-volume, and increase the industry’ profits.”

“A company will say: ‘ We want to use this IP with this foundry.’ I say I won’t make an SOC if I know it won’t work, adds Harding, “there’s a mind-boggling amount of waste with every SOC. Finding these variables and the waste in the ecosystem is our core competence.”

“On a chip half of it is RTL. There’s little point squeezing another 2% of performance out of the RTL but the other half is SRAM which we can improve in size and performance – I have 150 people developing SRAM IP.”

“In the post-20nm business model, how can we lower the bar without giving away fundamental IP?,” asks Harding, “one way is MPW (multit-project wafer) which reduces prototype cost by up to 90%. It costs about $100,000. it about one or two weeks to get an MPW run organized. eSilicon has reduced this to 15 minutes with an on-line tool which delivers a quote and the customer can go to a foundry and get it made. That tool reduces 40 hours of engineering work to 15 minutes.”


Comments

2 comments

  1. Says Harding, “there are a series of products we are displaying on-line for free.

    What Products? Where?

    Harding is talking about “non-differentiated IP,” therefore you could suppose that he’s posted some “non-differentiated IP” somewhere on the web?

    How about a definition of “non-differentiated IP” and “fundamental IP” to set the context more clearly?

    Conclusion: Catchy title, deficient article.

  2. I don’t quite get it – 40 hours of engineering work is not exactly a big deal in the overall scheme of things to generate a few prototype devices, when the original design work can run into many thousands of engineering hours.

Leave a Reply

Your email address will not be published. Required fields are marked *

*