ARM Fancies FD-SOI

ARM is enthusiastic about the potential of FD-SOI – STMicroelectronics’ process which is getting massive backing from the French government.”We have been looking at FD-SOI, it’s a very neat solution to providing more performance and lower power in a planar transistor,” Simon Segars, CEO of ARM, told EW.

“I’ve seen some of the results ST have achieved and they’re really impressive,” added Segars, “and I’ve seen chips running on the bench and, from the performance and power perspective, it’s very impressive.”

The next bulk CMOS process step for ARM is from 28nm to 20nm. “There are people doing production designs at 20nm,” said Segars.

Does he expect to see 3GHz ARM cores at 20nm?

“I think that’s come from TSMC who have done some early tape-outs of 20nm test chips so we can prepare the ground,” said Segars,

20nm is posing a dilemma for some users.

“A lot of people are looking at the potential cost uplift of 20nm weighing against the power and performance benefits and then deciding whether they should wait for 14nm,” said Segars, “the big thing at 20nm is the use of double patterning. If you have to put the wafer through the machine twice it’s going to cost more.”

ARM’s first move to finfet transistors comes at the 14nm node. “We’re at early stage evaluation of the technology,” said Segars, “we have taped out a number of test chips.”

“The PIPD people often run early tape-outs of ARM processors to get a feel of what the processes will deliver,” added Segars, “and to provide feedback on what we think the processes will deliver.”

ARM is already receiving revenue from server chips. “Q2 was a very busy month for ARM in servers Applied Micro and Calxeda announced design wins and AMD said they’re going to build Seattle using eight Cortex A57s each running at 2GHZ.”

If Segars goes on as he started he will have a distinguished tenure as CEO of ARM. At his first quarterly earnings call yesterday he announced profits up 30%, revenues up 24% and a record quarter for cash generation – adding nearly £100 million to the coffers which now hold £613 million in cash.


Comments

8 comments

  1. If I may be so bold as to trespass on your and Ian’s conversation, Mike, I would point to LETI’s belief that it scales to 10nm.
    http://www-leti.cea.fr/en/content/download/1856/24514/file/02%20Leti%20Day_M.Vinet%20FDSOI.pdf

  2. Ian, whilst I agree FinFETs are in no way easy, there are fundamental problems with the scaling of FD-SOI that I cannot discuss here. If you look at various roadmaps you will find it suddently goes missing for this very reason.

  3. @Mike : The node naming is even more of a joke than that, because going by the “real” definition (metal half-pitch) these are 32nm processes, not even 20nm, certainly not 14nm — 28nm was 40nm by the same measure, but at least that was only lying by one process node, not two or three 😉

    I don’t think there are any fundamental killer problems with FDSOI any more than with FinFET, both have significant differences with traditonal bulk CMOS which need to be overcome — anyone who thinks that manufacturing consistent bulk FinFETs is easy compared to manufacturing consistent UTBB SOI wafers doesn’t understand the issues. The problems are different for the two and they each have advantages and disadvantages, but both are a big jump forward over bulk planar. Intel likes FinFETs for its own very good reasons, which don’t apply to a large part of the industry.

    A Chinese colleague told me that TSMC’s “16nm FinFET” process is the same as all the others, but they couldn’t call it “14nm” because in Chinese “four” sounds like “death”, and “fourteen” is even worse because it sounds like “go to death”…

  4. Well, Mike, I knew that Intel didn’t invent it, I just said Intel likes it. And Intel’s example has a powerful effect on the rest of the industry. Nonetheless GloFo and IBM are going for FD-SOI as well as bulk and finfet. And then there’s finfet on SOI. It’s an interesting time in the industry with a proliferation of process options after a long period of consensus on bulk CMOS. But Intel is not always right e.g. It was slow to change from NMOS to CMOS.

  5. @Ian: the whole node naming is now in disarry almost to the point of bringing the industry into disrepute. At 14nm you are are correct for TSMC and GF (as far as I can ascertain) but remember Samsung have some via spacing tricks and Intel have traditionally been able to squeeze M2 and M3 (and just recently M4) tighter by about 12.5% c.f. M1 due to their design rules so there is no reason to believe this won’t be the case at 14nm as well. Intel will thus still have significant size and speed advantages over the others whilst Samsung could possibly overtake TSMC for second place on performance provided they can yield better than they have recently.

    @David: Intel didn’t invent FinFET, Hu works for TSMC and as far as I am aware has never received Intel funding. But when Intel, TSMC, Samsung, GF, UMC and even IBM go for the same technology (albeit IBM’s and possibly UMC’s is FinFET on SOI), doesn’t that perhaps indicate that they are not ‘rolling on their backs’ but have all realised the fundamental technical problem with FD-SOI that no amount of public funding is going to sucessfully overcome..

  6. Of course “14nm” (FDSOI or FinFET) really means “20nm metal stack with better transistors” — both are double patterned for the finest pitch (64nm) metal (typically 2-3) and via layers, the higher pitch (80nm) metal/via and poly/local interconnect are single-patterned.

    So the cost is similar to 20nm bulk but the performance (speed, power) is considerably better, this is why many people are considering skipping 20nm bulk (speed/power improvement not really worth the cost) and going to “14nm” only a year or so later.

    The next process (“10nm”, which means “14nm with better transistors”) will probably need triple patterning on the fine-pitch (48nm) metal/via and double-patterning on the higher-pitch (64nm) metal/via/poly/local layers, which means a huge increase in the number of the most expensive masks and decrease in throughput.

    But having played the one-off FDSOI/FinFET card already the power and speed improvement is likely to be smaller compared to “14nm” (similar case to 20nm bulk over 28nm), and combined with the huge design and NRE issues this suggests that not many designs will switch to this.

    Unless the EUV fairy finally delivers what has been promised for the last 10 years, which seems unlikely…

  7. I am enthusiastic about it, Mike. The semi industry has always been about better ideas replacing the incumbent idea. Just becos Intel likes finfet doesn’t mean the rest of the industry should roll on its back and put its paws in the air.

  8. Wouldn’t you be enthusiastic about something with so much subsidy attached to it ? Even IMEC have caved in and taken a bite of the FD-SOI Ponzi pie.

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