The 28nm Twilight Zone

The 28nm node has created a ‘twilight zone’ for mixed signal designers, says Ravi Subramanian, CEO of Berkeley Design Automation (BDA).

The pressures to shrink have never been greater. “Half of all designs will be below 65nm this year and 60% of fab capacity will be under 40nm,” says Subramanian. Demand for 28nm has surprised everyone.

Meanwhile the proportion of chips with analogue content, and the proportion of analogue circuitry to digital circuitry on chips are both rapidly increasing which means, says Subramanian that: “Analogue has to go into high volume at the same time as digital. There is no choice.”

“Mixed signal circuit yield is a major bottleneck in achieving volume production of 28nm ASSPs,” says Subramanian, “characterizing the performance of 28nm mixed signal designs in the presence of uncertainty is one of today’s biggest challenges.”

There are eight challenges: complexity, parasitics, device noise, corner spread, designing for low voltages, restricted design and design for yield.

“At 130nm designers could memorise the design rules. It would make an interesting TV show to see people trying to remember them at 28nm” he says, “electrical analysis has to be completely re-tooled.”

Device noise shot up 60% during the transition from 65nm to 45nm; characterization requirements go up 20x at 28nm over 40nm.

In view of the complains of CEOs from Qualcomm, Nvidia and Altera about the lack of Q1 28nm IC supply, does he see any reason why things may improve?

“Once they’re are at a certain point on the learning curve companies build out massive capacity,” said Subramanian.

Asked if they’d reached that point yet, Subramanian said he thought they had.