GloFo Looks For 7nm Leadership

A pretty big shift could be about to happen in the semiconductor industry – IBM’s scientific prowess could be about to be unleashed on the market.

GlobalFoundries is aiming to take industry process technology leadership at the 7nm node.

For the first time, GloFo now reckons it can take industry process leadership using a proprietary, in-house developed process technology , and this is thanks to the IBM acquisition.

“The IBM acquisition gave us people experienced in leading edge development,” GLoFo’s CTO Gary Patton tells me, ” the people who developed 45nm, 32nm, 22nm and 14nm are the same people who are working on 7nm.”

As well as IBM’s process experts GloFo is also benefitting from the Albany Nanotechnology Centre who his still run by IBM but which is currently “focussing on Malta” says Patton.

“Malta (one of GLoFo’s New York fabs) is high yield on 14nm, that gives me a very solid baseline to do the next node,” said Patton.

A major step towards achieving an industry-leading process at 7nm is a 60% shrink in the 14nm to 7nm transition.

When I asked how this was achieved, Patton replied: “We’re shrinking the pitches pretty aggressively.”

Under the terms of the IBM-GloFo deal 50% of Albany’s effort is going to support Malta with the other 50% pursuing pathfinding.

GLoFo’s 7nm process is so aggressive that, says Patton, it will deliver lower wafer cost even if EUV is delayed and they have to use multiple patterning. Patton reckons that EUV will be used in production in 2020 with “small usage in the 2018/19 timeframe.”

If GloFo can pull this off, it could have a big effect on the semiconductor industry with a fourth leading-edge process technology exponent in the industry along with Intel, TSMC and Samsung.

The net effect of another source of leading edge capacity could prove to be a powerful de-consolidating force in an industry which has recently shown trends towards consolidation.


Comments

3 comments

  1. I think you hit the nail on the head, Terry, it’s scaling interconnect where die shrinks can still be made.

  2. I’m curious about where it will all end, whether technical or economic limits will end the shrinking geometries. With lowest cost per transistor somewhere above 20nm then what’s the market for 7nm? From my limited understanding it can only be the top end ICs where speed per watt trumps cost considerations. Or will 3D chip stacks take over and leave Moore’s law dangling at the point where interconnects become the dominant factor?

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