5th RISC-V Workshop November 29-30, 2016
The goals of the workshop are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set. The workshop fee will include two breakfasts, two lunches, and an evening reception nearby at the iconic Computer History Museum.
Each workshop has helped both document the rapidly rising popularity of RISC-V and boosted it further due to the information shared and collaborations formed at the event. Please join us!
Workshop registration details can be found here.
Preliminary Agenda
Tuesday, November 29th, 2016
| Time | Event | Speaker, Affiliation | Media |
| 8:00am | Networking Breakfast | ||
| 8:45am | 5th RISC-V Workshop Introduction | Rick O’Connor, RISC-V; Dom Rizzo, Google | |
| 9:00am | RISC-V @ UC San Diego | Michael B. Taylor, UC San Diego | |
| 9:15am | Updates on PULPino | Florian Zaruba, ETH Zurich | |
| 9:30am | SiFive FE300 and low-cost HiFive Development Board | Jack Kang, SiFive | |
| 10:00am | Rapid silicon prototyping and production for RISC-V SoCs | Neil Hand, Codasip | |
| 10:30am | Networking Break | ||
| 11:00am | Extending RISC-V for Application-Specific Requirements | Steve Cox, Synopsys | |
| 11:30am | A memory model for RISC-V | Muralidaran Vijayaraghavan, MIT | |
| 12:00pm | A Memory Consistency Model for RISC-V | Caroline Trippel, Princeton University | |
| 12:30pm | Networking Lunch | ||
| 1:30pm | Keynote Address: Trust, Transparency and Simplicity | Eric Grosse, Google | |
| 2:00pm | RISC-V Foundation Update | Rick O’Connor, RISC-V Foundation | |
| 2:15pm | RISC-V Marketing Committee Update | Arun Thomas, BAE Systems | |
| 2:30pm | RISC-V Technical Committee Update | Yunsup Lee, SiFive | |
| 2:45pm | Rocket Chip Foundation: a nonprofit foundation for hosting open-source RISC-V implementations, tools, code | Yunsup Lee, SiFive | |
| 3:00pm | Networking Break | ||
| 3:30pm | 128-bit addressing in RISC-V and security | Steve Wallach, Micron | |
| 4:00pm | The Challenges of Securing and Authenticating Embedded Devices and a Suggested Approach for RISC-V | Derek Atkins, SecureRF | |
| 4:15pm | Sanctum: Minimal Hardware Extensions for Strong Software Isolation | Ilia Lebedev, MIT | |
| 4:45pm | Joined up debugging and analysis in the RISC-V world | Gajinder Panesar, UltraSoC | |
| 5:15pm | Poster / Demo Previews ~ 2min per presenter | ||
| 5:45pm | Transition to Reception | ||
| 6:00pm | Networking Reception, Posters Sessions and Demos | Hosted by Google at the Computer History Museum | |
| 9:00pm | Adjourn for the Day |
Wednesday, November 30th, 2016
| Time | Event | Speaker, Affiliation | Media |
| 8:00am | Networking Breakfast | ||
| 9:00am | OpenHPC System Architect: An Open Toolkit for Building High Performance SoCs | Farzad Fatollahi-Fard, Lawrence Berkeley National Lab | |
| 9:30am | “V” Vector Extension Proposal | Krste Asanovic, UC Berkeley & SiFive | |
| 10:00am | Towards Thousand-Core RISC-V Shared Memory Systems | Quan Nguyen,MIT | |
| 10:15am | SCRx: a family of state-of-the art RISC-V synthesizable cores | Alexander Redkin, Syntacore | |
| 10:30am | Networking Break | ||
| 11:00am | Enabling hardware/software co-design with RISC-V and LLVM | Alex Bradbury, lowRISC | |
| 11:30am | VM threads: an alternative model for virtual machines on RISC-V | Ron Minnich, Google | |
| 12:00pm | Enabling low-power, smartphone-like graphical UIs for RISC-V SoCs | Michael Gielda, Antmicro | |
| 12:30pm | Networking Lunch | ||
| 1:30pm | A Fast Instruction Set Simulator for RISC-V | Maxim Maslov, Esperanto | |
| 2:00pm | Go on RISC-V | Benjamin Barenblat, Michael Pratt, Google | |
| 2:15pm | A Java Virtual Machine for RISC-V: Porting the Jikes RVM | Martin Maas, UC Berkeley | |
| 2:30pm | YoPuzzle: A mRISC-V development platform for next generations | Elkim Roa, Universidad Industrial de Santander | |
| 2:45pm | RISC-V Community needs Peripheral Cores | Elkim Roa, Universidad Industrial de Santander | |
| 3:00pm | Networking Break | ||
| 3:30pm | Sub-microsecond Adaptive Voltage Scaling in a 28nm RISC-V SoC | Ben Keller, UC Berkeley | |
| 4:00pm | Reprogrammable Redundancy for Cache Vmin Reduction in a 28nm RISC-V Processor | Brian Zimmer, UC Berkeley; NVIDIA | |
| 4:30pm | 5th RISC-V Workshop Conclusion | Rick O’Connor, RISC-V Foundation; Dom Rizzo, Google | |
| 4:45pm | End of Workshop |