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row-start col-xs-12 row-end agenda-section agenda |
Automotive | Custom Implementation & AMS | ||
General Sessions | IP | ||
Lunch & Learn | Machine Learning | ||
Networking Opportunities | Physical Implementation | ||
RTL Implementation | Signoff & Characterization | ||
Test | User Content Reviewed by the Technical Committee | ||
Verification Continuum |
March 21, 2018 | |||||
7:30 am - 6:00 pm | Lobby | Registration [More Info] | |||
9:00 am - 10:30 am | Mission City Ballroom | Keynote - At the Heart of Impact [More Info] Dr. Aart de Geus, Chairman & co-CEO, Synopsys | |||
11:00 am - 11:45 am | Great America K | Device Parasitic Handling and Other Challenges in RF Enablement for GLOBALFOUNDRIES 14nm PDK [More Info] Cole Zemke, GLOBALFOUNDRIES Jagannathan Vasudevan, Member of Technical Staff, GLOBALFOUNDRIES | |||
11:00 am - 11:45 am | Ballroom H | Does ISO 26262 Scale to Large, Complex SoCs? [More Info] Kevin Rich, NVIDIA | |||
11:00 am - 11:45 am | Mission City 1 | Emerging Node Design with IC Compiler II [More Info] Mindy Kao, Synopsys | |||
11:00 am - 11:45 am | 203/204 | Fast Design Closure of Dense-Mesh Global Clock Trees Using HSPICE and MATLAB [More Info] Jason Ferrell, MTS Design Engineer, AMD | |||
11:00 am - 11:45 am | 210 | Managing the Cost of Test in an Environment of Increasing Design Complexity Using Rapid and Predictable Quality Tests [More Info] Adam Cron, Synopsys | |||
11:00 am - 11:45 am | Great America J | Next-Generation Signoff Power Analysis and ECO - A Technology Preview [More Info] Haroon Chaudhri, Synopsys | |||
11:00 am - 11:45 am | 209 | Prototyping Lower Power Intent for System Validation [More Info] Sharath Duraiswami, Synopsys | |||
11:00 am - 11:45 am | Hall A2 | Realizing Faster Simulations/Diagnosis with VCS' New Parallel Simulation and UFE Technology [More Info] Pine Yan, Sr. Mgr, Hardware Engineering, NVIDIA | |||
11:00 am - 11:45 am | Hall A3 | Use of Synopsys Virtualizer to Shift Left Software Development of Solid-State Drives [More Info] | |||
11:00 am - 11:45 am | Ballroom G | Using IC Compiler II (Design Planning) to Address Challenges in DCT Floorplanning [More Info] Elodie Fechino, Senior Design Engineer, NVIDIA Rahul Nodu Shivananda, NVIDIA | |||
11:45 am - 12:30 pm | Great America K | 3D Extraction: What, Why, Where? [More Info] Krishnakumar Sundaresan, Synopsys | |||
11:45 am - 12:30 pm | 210 | Evaluation of TetraMAX II for Small Digital Designs in Mixed Signal Applications [More Info] Richard Illman, Member of Technical Staff, Dialog Semiconductor | |||
11:45 am - 12:30 pm | Hall A3 | Expanding the Scope of Virtual Prototyping Use Cases with Virtualized Interfaces [More Info] Phalguna Devalaraju, Sr. Staff Engineer, Qualcomm | |||
11:45 am - 12:30 pm | 203/204 | HSPICE, FineSim, Custom WaveView Updates and a Tutorial on SPICE Acceleration for Analog Circuits Using FineSim SPICE [More Info] Gim Tan, Synopsys | |||
11:45 am - 12:30 pm | Hall A2 | Improving Simulation Throughput with Fine-Grained Parallelism (FGP) [More Info] Kiran Maiya, Synopsys | |||
11:45 am - 12:30 pm | Ballroom G | Improving Timing Convergence Efficiency Combining Bottom-Up and Top-Down Methodologies [More Info] | |||
11:45 am - 12:30 pm | 209 | Out-of-the-Box Prototyping Enabling Interactive Software Development [More Info] Achim Nohl, Synopsys Neil Songcuan, Synopsys | |||
11:45 am - 12:30 pm | Mission City 1 | Placement and Routing Algorithms for Sequential Chains Implementation [More Info] | |||
11:45 am - 12:30 pm | Great America J | Signoff Power Analysis Driven PrimeTime ECO for Best PPA - Accelerated by Machine Learning [More Info] Vivek Ghante, Synopsys Nahmsuk Oh, Synopsys | |||
11:45 am - 12:30 pm | Ballroom H | Using Synopsys Z01X to Fasten the Fault Injection Campaign of a Fully Configurable IP [More Info] Mohan Krishnareddy, Solutions Architect, Arteris | |||
12:30 pm - 2:00 pm | Mission City Ballroom | Lunch & Learn: Achieving Best QoR and Fastest TAT with Synopsys' Design Platform [More Info] | |||
12:30 pm - 2:00 pm | Hall A1 | Lunch & Learn: SoC Leaders Verify with Synopsys [More Info] Dr. Johannes Stahl, Synopsys | |||
12:30 pm - 2:00 pm | Hall D | Networking Lunch [More Info] | |||
2:00 pm - 2:45 pm | 203/204 | Accelerating EM/IR and Timing Closure Using CustomSim and CustomSim Circuit Check (CCK) Static ERC Analysis [More Info] Raed Sabbah, Staff CAD Engineer, Micron | |||
2:00 pm - 2:45 pm | Ballroom G | Design Compiler QOR and Productivity Improvements [More Info] Abhijeet Chakraborty, Synopsys | |||
2:00 pm - 2:45 pm | Hall A3 | Introduction to Reset Domain Crossings [More Info] Tanveer Singh, Synopsys | |||
2:00 pm - 2:45 pm | 210 | Is the Default TetraMAX Transition Fault List Adequate? [More Info] Speaker: Richard Illman, Member of Technical Staff, Dialog Semiconductor | |||
2:00 pm - 2:45 pm | Ballroom H | ISO 26262: What's Required for Safety-Critical Semiconductor Designs? [More Info] Mary Ann White, Synopsys | |||
2:00 pm - 2:45 pm | Great America J | Power Estimation Correlation to Silicon Using an Advanced Low Power Holographic Processing Unit Chip [More Info] Anand Iyer, Senior Design Engineer, Silicon Development, Microsoft Ted Williams, Principal, Silicon Engineering, Microsoft Tim Balbekov, Silicon Design Engineer II, Microsoft | |||
2:00 pm - 2:45 pm | Hall A2 | Speed is the Name of the Game, Every Second Counts! (Simulation Acceleration Using VCS FGP Technology) [More Info] Debashis Biswas, ASIC Verification Lead, NVIDIA | |||
2:00 pm - 3:30 pm | Mission City 1 | Panel: Extreme Physical Verification Productivity Gains with IC Validator [More Info] Henry Bonges, Layout Automation Consultant, IBM Tom Quan, TSMC James Chen, Senior Director, Advanced Technology Group, NVIDIA Henry Selvaraj, Principal Engineer, Juniper Networks Hiroaki Hanamitsu, Senior CAD Engineer, Socionext Inc. | |||
2:00 pm - 3:30 pm | 209 | What’s New in Emulation and Why: Technology Trends and Drivers in Emulation [More Info] Dhiraj Goswami, Synopsys | |||
2:45 pm - 3:30 pm | Great America J | A Bottom-Up Methodology to Evaluate Silicon Power Consumption for a Large Number of Application-Specific Use Cases [More Info] Gur Samrao, Broadcom | |||
2:45 pm - 3:30 pm | Hall A3 | Comprehensive SDC-based Clock Domain Crossing Verification [More Info] Sean O'Donohue, Synopsys | |||
2:45 pm - 3:30 pm | 210 | DFTMAX Ultra's Advanced Compression Logic "FIDO: Fan In Direct Out" [More Info] | |||
2:45 pm - 3:30 pm | 203/204 | Dynamic ESD Analysis for Design Optimization and ESD Sign-off [More Info] | |||
2:45 pm - 3:30 pm | Hall A2 | Functional Coverage in SystemC [More Info] Mark Glasser, NVIDIA | |||
2:45 pm - 3:30 pm | Ballroom H | Orchestrating Functional Safety in Today's Automotive SoCs [More Info] | |||
2:45 pm - 3:30 pm | Ballroom G | Techniques for Implementing Power Efficient Application Specific Large Counters for Better Area and Performance [More Info] | |||
3:45 pm - 4:30 pm | Hall A2 | A Pragmatic Verification Coverage Strategy for 3D NAND Flash Memory Component: A Step Closer to Objective Design Sign-off [More Info] | |||
3:45 pm - 4:30 pm | 209 | A Pre-Silicon Emulation Platform for Early Software Development of Multi-Mode Modem SoC [More Info] | |||
3:45 pm - 4:30 pm | Hall A3 | Achieving Faster Testbench Development Turnaround Using Partition Compile [More Info] Dharav Dantara, Senior Verification Engineer, Xilinx | |||
3:45 pm - 4:30 pm | Ballroom G | Automated RTL-2-GDS Flow to Achieve Industry-Leading PPA Results for State-of-the-Art Arm CPU Design at 10nm Technology Node [More Info] | |||
3:45 pm - 4:30 pm | Ballroom H | Ethernet Time-Sensitive Networking for Autonomous Vehicle and ADAS SoCs [More Info] John Swanson, Synopsys | |||
3:45 pm - 4:30 pm | Mission City 1 | PG Network Creation and Analysis for Advanced Node Designs [More Info] John Chen, Synopsys | |||
3:45 pm - 4:30 pm | Great America K | Robust Automated Solution for Performing Schematic ESD Checks [More Info] | |||
3:45 pm - 4:30 pm | Great America J | SRAM Dynamic Power Validation Methodology [More Info] Sudha Vasu, Senior SRAM Circuit Designer, NVIDIA | |||
3:45 pm - 4:30 pm | 210 | TetraMAX Cell-aware Technology, Library Characterization, ATPG and Diagnostics [More Info] Brian Archer, Synopsys Steve Palosh, Synopsys | |||
3:45 pm - 4:30 pm | 203/204 | Vector Independent Timing Verification for Full Custom Memories Using Verilog-A and CustomSim [More Info] Ramasamy Adaikkalavan, Staff Engineer , Qualcomm | |||
4:30 pm - 5:15 pm | 210 | A Method to Debug LBIST Mode SSA/TF Silicon Failure Accurately Using Scan-Through-TAP {STT Mode} [More Info] Vinay Kumar, STMicroelectronics | |||
4:30 pm - 5:15 pm | 203/204 | A Simulation-Based Failure Rate Analysis for Automotive Applications Using CustomSim [More Info] Radu Iacob, Sr. Manager of Quality Assurance, Kilopass | |||
4:30 pm - 5:15 pm | Ballroom G | Arm DynamIQ - Redefining Arm Multicore Compute - A Case Study of Application Specific Configurations and Implementation Challenges Across Multiple Nodes [More Info] Himanshu Chopra, Senior Design Engineer, Arm | |||
4:30 pm - 5:15 pm | Mission City 1 | Block Level Floorplan Debug with IC Compiler II [More Info] Pete Churchill, Synopsys | |||
4:30 pm - 5:15 pm | Great America J | Cell Electromigration Analysis with PrimeTime PX [More Info] Anasuya Raghunathan, Synopsys | |||
4:30 pm - 5:15 pm | Great America K | Improving Non-Uniform Standard Cell Density to Satisfy Post Placement Window-Based Density Constraints [More Info] | |||
4:30 pm - 5:15 pm | Hall A3 | Ready, SoC, Go: Automated Testbench Generation and Protocol Performance Verification to Fast-track your SoC [More Info] Bernie DeLay, Synopsys | |||
4:30 pm - 5:15 pm | 209 | Regression Testing for Verification of Advanced CPU Subsystems Using Fast Emulation [More Info] Theertha Somashekharappa, Synopsys Eric White, Senior Member of Technical Staff, Cores Verification and Emulation, AMD Syed Obaidulla, Senior Member of Technical Staff, Technical Lead DFT Verification & Emulation, AMD | |||
4:30 pm - 5:15 pm | Hall A2 | SMARTer Coverage Closure with Verdi - A Primer on Verification Planning and Coverage Analysis [More Info] Bart Thielges, Synopsys | |||
4:30 pm - 5:15 pm | Ballroom H | TSMC Automotive Design Enablement Platform [More Info] Tom Quan, TSMC | |||
5:15 pm - 7:00 pm | Hall B | SNUG Pub [More Info] | |||
March 22, 2018 | |||||
8:00 am - 6:00 pm | Lobby | Registration [More Info] | |||
9:00 am - 10:00 am | Mission City Ballroom | Keynote - The Future of Mobility [More Info] Henrik Fisker, Chairman & CEO, Fisker Inc. | |||
10:30 am - 11:15 am | Hall A2 | Accelerated Plan Driven Verification of MIPI SPMI Protocol [More Info] Sneha Patel, Broadcom | |||
10:30 am - 11:15 am | Great America J | Accelerating Asynchronous Clock Domain Crossing Timing Verification and Design Implementation with PrimeTime [More Info] Frank Hsu, Principal Design Engineer, SK Hynix Memory Solutions | |||
10:30 am - 11:15 am | 203/204 | Accelerating High-Speed Datapath Design Verification in NAND Flash Memories Using FineSim VCS [More Info] Frank Tsai, Techonologist, Western Digital | |||
10:30 am - 11:15 am | Mission City 2 | Bitcoin 2.0 - Updates to Synopsys Low Power Flow [More Info] Antonio Dimalanta, Synopsys | |||
10:30 am - 11:15 am | Ballroom H | Bringing Digital Intelligence to the Design Platform [More Info] Stelios Diamantidis, Synopsys Joe Walston, Synopsys | |||
10:30 am - 11:15 am | Hall A3 | Formal Verification of Software Configurable Silicon for SDN [More Info] Saurabh Shrivastava, Cavium | |||
10:30 am - 11:15 am | Great America K | Implementing Artificial Intelligence in Embedded Vision Applications [More Info] Gordon Cooper, Synopsys | |||
10:30 am - 11:15 am | 210 | SpyGlass DFT ADV Early Testability Analysis [More Info] Fadi Maamari, Synopsys | |||
10:30 am - 12:00 pm | Mission City 1 | Panel: EUV, High-NA, Metallurgy and FinFET++ - Where We Go from Here for Next-Generation Design [More Info] | |||
11:15 am - 12:00 pm | 203/204 | Accelerating Full Coverage and Functional Safety Verification of Mixed-Signal Designs Using CustomSim and VCS AMS [More Info] Randall Nubling, Synopsys | |||
11:15 am - 12:00 pm | Mission City 2 | An Approach for Consistent Hierarchical Implementation and Verification of UPF Designs [More Info] Amol Herlekar, Synopsys Viswanath Ramanathan, Synopsys | |||
11:15 am - 12:00 pm | 210 | DFT Connectivity Validation on Complex SoCs Using SpyGlass DFT ADV Connectivity Check [More Info] Hong Dai, Qualcomm | |||
11:15 am - 12:00 pm | Ballroom H | Full Chip FinFET Self-Heat Prediction Using Machine Learning [More Info] Chintan Shah, NVIDIA | |||
11:15 am - 12:00 pm | Great America K | One-Time Programmable NVM IP for High-Reliability, Secure Mobile and IoT SoCs [More Info] Ken Wagner, Synopsys | |||
11:15 am - 12:00 pm | Great America J | Static Timing Analysis of Custom Mixed-Signal Circuits [More Info] Lily Aggarwal, Principal Hardware Engineer, Microsoft | |||
11:15 am - 12:00 pm | Hall A2 | Using the AMBA VIP to Integrate a C/C++ Processor Model in the RTL Simulation, and Debug with Verdi [More Info] Lu Hao, Software Engineer, NXP | |||
11:15 am - 12:00 pm | Hall A3 | Who Will Guard The Guards? [More Info] Mandar Munishwar, Sr, Staff Engineer, Qualcomm | |||
12:00 pm - 1:30 pm | Mission City Ballroom | Lunch & Learn: Synopsys Custom Design Platform: Accelerating Robust Custom Design [More Info] | |||
12:00 pm - 1:30 pm | Hall B | Lunch & Learn: Accelerating Time to Results with Synopsys' RTL-to-GDSII Platform [More Info] | |||
12:00 pm - 1:30 pm | Hall A1 | Lunch & Learn: IP With Near Zero Energy Budget Targets Machine Learning Applications [More Info] Navraj Nandra, Synopsys | |||
12:00 pm - 1:30 pm | Hall D | Networking Lunch [More Info] | |||
1:30 pm - 2:15 pm | Ballroom H | Supervised and Unsupervised Learning for Accelerating Verification Convergence [More Info] Manish Pandey, Synopsys | |||
1:30 pm - 2:20 pm | Ballroom G | FIFO as a Power Efficient Delay Device [More Info] Devendra Tripathi, IC Design Engineer, Broadcom | |||
1:30 pm - 2:20 pm | 203/204 | First Pass Silicon Success Using Custom Compiler [More Info] Varun Ramaswamy, Methodology and Physical Verification Lead, Seagate | |||
1:30 pm - 2:20 pm | Great America K | Next-Generation Low-Power Memory Interfaces [More Info] Brett Murdock, Synopsys | |||
1:30 pm - 2:20 pm | Great America J | PVT Optimization with CCS Scaling [More Info] | |||
1:30 pm - 2:20 pm | Mission City 2 | Strategies for Formality Success [More Info] John Busco, Director, Logic Design Implementation, NVIDIA | |||
1:30 pm - 2:20 pm | Hall A2 | SystemVerilog Virtual Classes, Methods, Interfaces and Their Use in Verification and UVM [More Info] Cliff Cummings, Sunburst Design | |||
1:30 pm - 2:20 pm | 210 | Using SpyGlass DFT ADV & DFTMAX Physical-Aware Test Point Insertion to Increase ATPG Efficiency [More Info] Sounil Biswas, Cavium Amit Madupu, Cavium | |||
1:30 pm - 3:10 pm | Mission City 1 | Best Practices for High-Performance, Energy Efficient Implementations of the Latest Arm® Processors in 7-nanometer FinFET (7FF) Process Technology Using Synopsys Design Platform [More Info] Joe Walston, Synopsys Deep Kanwar Singh Bhullar, Staff Design Engineer, Arm | |||
1:30 pm - 3:10 pm | Hall A3 | VC Formal Apps Expansion: Security, X-Prop and Registers Verification [More Info] Anders Nordstrom, Synopsys Iain Singleton, Synopsys Ravindra Aneja, Synopsys | |||
2:15 pm - 3:10 pm | Ballroom H | Panel: From Self-Driving Cars to Self-Driving Designs [More Info] Thomas Andersen, Synopsys | |||
2:20 pm - 3:10 pm | 203/204 | Development of Compatibility Flow Between Custom Compiler and Other Vendor Tools [More Info] Shuhei Nishida, Principal Engineer, Renesas | |||
2:20 pm - 3:10 pm | Mission City 2 | Formality Best Practices and Technology Update [More Info] Uday Dixit, Synopsys | |||
2:20 pm - 3:10 pm | Ballroom G | Glitch Scaler - A New Approach to Model Glitch Power in Logic Simulation [More Info] Jiu-Shang Yang, Sr. Technical Manager, MediaTek | |||
2:20 pm - 3:10 pm | 210 | Memory Test & Repair and Hierarchical Test of Interface IP for Enterprise and Automotive FinFET Based SoCs [More Info] Yervant Zorian, Synopsys | |||
2:20 pm - 3:10 pm | Great America J | SiliconSmart Update Tutorial [More Info] Ragini Suram, Synopsys | |||
2:20 pm - 3:10 pm | Great America K | System Design Secrets for Successful DDR3/4 & LPDDR4 Interfaces [More Info] Jason Monroe, Synopsys Michael Zieglmeier, Synopsys | |||
2:20 pm - 3:10 pm | Hall A2 | Tackling SystemVerilog and UVM Testbench Debug Challenges - Interactive Debug with Verdi and VCS [More Info] Brian Schneider, Synopsys | |||
3:30 pm - 4:15 pm | Mission City 1 | 22FDx IC Compiler II Body-Bias Interpolation and Correlation to PrimeTime [More Info] Haritez Narisetty, PMTS / Sr.Manager, GLOBALFOUNDRIES Ramya Srinivasan, MTS Design Enabkement, GLOBALFOUNDRIES | |||
3:30 pm - 4:15 pm | 203/204 | Custom Compiler Template-Based Design for Layout Automation [More Info] Jimmy Lin, Synopsys | |||
3:30 pm - 4:15 pm | Ballroom H | Data Driven Approaches to Improving Simulation Methodologies in Synopsys Mixed-Signal IPs [More Info] Mohan Mohan, Synopsys | |||
3:30 pm - 4:15 pm | Hall A2 | Extending Coverage Planning to Low Power Verification [More Info] Jason Ko, Broadcom | |||
3:30 pm - 4:15 pm | Hall A3 | Next Step of Formal Verification Utilization: Use and Development of Assertion Based Protocol Checkers [More Info] Yuri Tatarnikov, Principal Verification Engineer, SK Hynix Memory Solutions | |||
3:30 pm - 4:15 pm | Great America K | Next-Generation PCI Express and Accelerators (PCIe 5.0 & CCIX) [More Info] Richard Solomon, Synopsys | |||
3:30 pm - 4:15 pm | Great America J | PrimeTime Accuracy for Advanced Technology Nodes [More Info] Gagik Ohanyan, Synopsys | |||
3:30 pm - 4:15 pm | Mission City 2 | Salient Features in IEEE 1801-2015 (UPF 3.0) to Specify Power Intent for SoCs [More Info] Viswanath Ramanathan, Synopsys | |||
3:30 pm - 4:15 pm | Ballroom G | Synopsys FPGA Platform Enabling Planning to Synthesis [More Info] Paul Owens, Synopsys | |||
4:15 pm - 5:00 pm | Ballroom G | Building Smart SoCs: Using Virtual Prototyping for the Design and SoC Integration of Artificial Intelligence Accelerators [More Info] Tim Kogel, Synopsys | |||
4:15 pm - 5:00 pm | Hall A2 | Catch X-Propagation Issues at RTL in the Presence of UPF - Using VCS X-Prop with Native Low Power [More Info] Karan Brar, Synopsys | |||
4:15 pm - 5:00 pm | Mission City 1 | IC Compiler II Release Update [More Info] Aditi Vijaykumar, Synopsys | |||
4:15 pm - 5:00 pm | 203/204 | Physically-Aware Simulation and Electrical Analysis During Layout [More Info] Sandrine Rothblez, Synopsys | |||
4:15 pm - 5:00 pm | Great America J | PrimeTime Reporting Runtime & Productivity Improvements [More Info] Joseph Thomas, Synopsys | |||
4:15 pm - 5:00 pm | Hall A3 | Shift Left in Verification - Formal Verification Case Study on USB Hub 3.1 IP [More Info] Garett Choy, Synopsys Ravindra Aneja, Synopsys | |||
4:15 pm - 5:00 pm | Ballroom H | Using Machine Learning to Improve Overall Engineering Productivity, Quality, and Cost - Synopsys Case Studies [More Info] Arun Venkatachar, Synopsys | |||
4:15 pm - 5:00 pm | Mission City 2 | What Advanced Node Support Means to Synthesis, What's Changing and What it Promises to Deliver [More Info] Carlos Abraham, Synopsys | |||
5:00 pm - 6:30 pm | Hall B | Awards and SNUG After Party [More Info] |
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