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RISC-V Processor Designs Emerge

By   02.03.2021 0

Open source hardware based on RISC-V processor designs has a bit of drift compared to its software counterpart: The framework freezes instruction set architecture (ISA) as a durable long-term component. Here, ISA is the vocabulary that processors understand, so software is written in that vocabulary. How software is coded in that language tells the processor what to do.

Anyone can take the RISC-V ISA and design other aspects such as extensions. What’s the hardware approach has in common with open source software is that RISC-V is free of IP entanglements, and participants can share the results of their design efforts.

In short, RISC-V allows design engineers to innovate, providing them the freedom of choice.


The open source movement that transformed software development is gaining traction among hardware developers. Early efforts centered on the RISC-V architecture are leading the way. We explore the promise and the pitfalls of open hardware development in our upcoming Open Source Special Project.

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By Shingo Kojima, Sr Principal Engineer of Embedded Processing, Renesas Electronics  03.26.2024

Krste Asanovic, SiFive’s co-founder and chief architect, clarified RISC-V’s standing in the open source hardware world during a CES 2021 panel discussion. “RISC-V isn’t an open source processor,” Asanovic noted. “Instead, it’s an open standard for developing a processor.” Hence, the specification is open, and anybody can implement it.

That’s akin to a micro-architecture license that allows a processor developer to customize the exact way it wants to optimize a processor design. Take, for example, Western Digital, a storage device maker that developed its own controller processors for solid-state drive designs. The goal was optimizing the controller interface to both the main CPU and flash memory.

Western Digital’s SweRV Core EL2 core is designed to replace state machines and other logic functions in system-on-chips.

During the RISC-V Summit 2020, Western Digital showcased a flash controller based on its open source RISC-V-enabled SweRV cores. Ted Marena, the company’s senior business director for RISC-V, said Western Digital is releasing the RISC-V cores to the open source community.

“While we had invested in developing the cores, it’s not really the core that is secret,” he said. “Instead, it’s the stuff built around the core like interface to host processor that matters the most.” Added Marena: “How you interface the flash on the other side can be the real differentiator.” Making cores available to the open source community also attracted outside contributions that could ultimately lead to design enhancements, he added.

CPU Core Choices

While companies such as Nvidia and Western Digital are building chips based on their own RISC-V cores, others can license pre-built configurable cores. For that, they approach companies like SiFive, which views its role as analogous to Red Hat for Linux, providing a variety of licensable RISC-V cores that processor designers can incorporate into their commercial silicon.

While that’s a significant part of the company’s business, SiFive also provides services that allow engineers to take their processor design through to chip fabrication.

SiFive’s E31 core is targeted at IoT, storage, and industrial applications.

According to Art Swift, president and CEO of AI chipmaker Esperanto Technologies, more designers are moving to RISC-V as they pursue different business models. “Instead of a handful of MCUs, all based on the same core, RISC-V provides an opportunity to license a greater variety of cores from multiple vendors.”

There are currently at least seven commercial providers of RISC-V cores.

With the existing proprietary ISA, managed by a single vendor, Swift said processor designs that do not address specific industry needs means customers are stuck with an ISA unless they acquire a costly architecture license permitting them to build custom cores. And reselling cores is no longer an option. That’s why few companies—like Apple—can afford that level of investment.

In the case of RISC-V, however, the architecture license is free. Users can either build their own core or choose an open source version. As Swift notes, having many core options is also critical for future-proofing designs.

Esperanto, an early adopter, packs more than 1,000 low-power RISC-V cores in a single chip to accelerate AI workloads in data centers.

Next Computing Revolution?

Nearly two decades ago, programmers considered Linux a niche technology, guessing it would go nowhere. We now see a redux in the hardware community, with startups building processors based on the RISC-V open standard, and venture capitalists scrutinizing chip upstarts.

Simultaneously, big players like Nvidia and Western Digital are also looking to RISC-V for large volume implementations.

RISC-V, which began as a research project, has come a long way as an evolving open standard for processor designs. As Swift noted, RISC-V isn’t about religious wars between instruction sets, as it was in the past.

Instead, it’s about innovation capacity and freedom of choice.

Also notable is growing momentum, infrastructure and a software ecosystem coalescing around RISC-V processor designs. The promise of open source hardware appears alive and well in the form of RISC-V open standard, perhaps ushering in the next computing revolution.

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