Description and Features
Our Universal Flash Storage (UFS) Controller IP is compliant with the latest JEDEC UFS v3.1 specification. The UFS standard is a high performance, low power serial interface that efficiently moves data between a host processor and mass storage devices.
When our UFS Controller IP is combined with in-house developed UniPro Controller IP and M-PHY IP, designers can easily integrate PHY and the controller with low risk and accelerate time-to market with our UFS IP solution.
Verification : IP Functionally is verified in NC – Verilog simulation software using testbench written in Verilog HDL
Features
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Compliant with the JEDEC UFS v3.1
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Backward compatibility JEDEC UFS v3.0 & v2.1
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TAG overlap/LBA overlap/Valid UPIU check
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Maximum DATA OUT = 64KB
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Maximum DATA IN = 64KB
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Maximum RTT number= 8
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CMD Queue Depth = 32
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HW Auto NOP IN Response
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HW Auto Query Response
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HW Auto Write Function
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Support HPB v1.0 (Host-aware Performance Booster)
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Support EHS (Extra Header Segment)
Deliverables
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User Manual
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Behavior model, and RTL codes
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Test patterns and Test Documentation
Benefits
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Write-protect options include permanent and power-on protection
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RMM-compliant synthesizable RTL design in Verilog
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Easy-to-use test environment
Applications
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IOT
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Automotive
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Storage
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Consumer
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Embedded
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Enterprise
