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VC Verification IP for HBM
Synopsys® VC Verification IP for HBM provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of HBM based designs.
Memory Model Certification
Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.
Highlights
- Native SystemVerilog/UVM
- Runs natively on all major simulators
- Runtime JEDEC and vendor part selection
- Verification plan and coverage
- Built-in protocol checks
- Verdi® protocol-aware debug and performance analyzer
- Back door memory access
- Bypass, fast-memory initialization
- Trace files and debug ports
- Multi channel environment
- Error injection and exceptions
Protocol Features
- JEDEC JESD23B rev 3.30
- HBM 3.0
- HBM1 and HBM2/2E modes
- IEEE Test port supported
- All commands - ROW/COLUMN commands sampling
- All mode register implementation
–Burst length BL2 and BL4
–All combination of read and write latencies - DBI read and DBI write
- Data masking (for write)
- Sequential and wrap addressing
- Refresh operation and corrupting the data if refresh not received
- Seamless read and write
- Bank group
- Frequency change and clock stop
- Pseudo channel
- Data read/write and command parity
- ECC support
- Data rate support up to 3.6Gbps per pin