Description and Features

Ethernet 800G MAC core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 10G MAC IP is proven in FPGA environment. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

Features

• Compliant with IEEE Standard 802.3-2018 specification
• Supports full duplex mode of operation
• Supports Standard 800Gbps Ethernet link layer data
• Supports 1024-bit CDMII interface
• Supports Programmable Inter Packet Gap (IPG) and Preamble length
• Supports MDIO (Clause 22 and Clause 45) Interface
• Supports start control character alignment
• Provides detailed statistics as per the specification
• Supports Jumbo Frame
• Supports Loopback functionality
• Supports transmit and receive FIFO interface
• Supports FCS(CRC) transmission and reception
• Supports Pause frame-based flow control
• Supports IEEE Standard 802.3az Energy Efficient Ethernet (EEE)
• Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
• Optional Wake-on-LAN support
• In house UNH compliance tested
• Optional support for TCP/IP offload
• Optional support for IEEE Standard 1588-2008 PTP
• Optional support for DMA on both transmits and receive side
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

• Customized licensing arrangement for organizations based at a singular location, guaranteeing exclusive usage rights.

• Flexible licensing option tailored for businesses with operations spread across multiple sites, facilitating extensive deployment.

• Permits incorporation of the IP Core into a solitary FPGA bitstream and ASIC, encouraging precise implementation.

• Provides unlimited access to the IP Core for integration into numerous FPGA bitstreams and ASIC designs, fostering boundless innovation and scalability.

Deliverables

• Verilog RTL design

• Seamlessly incorporating waivers into validation scripts for comprehensive Linting, CDC analysis, and Synthesis coverage

• Providing detailed and thorough reports offering profound insights into Linting, CDC analysis, and Synthesis methodologies

• Efficient utilization of IP-XACT RDL for the generation of address maps

• Consolidating firmware code and Linux drivers into a unified and coherent package

• Supplying extensive technical documentation comprehensively covering all aspects

• Establishing a Verilog Test Environment with intuitive integration of test cases for comprehensive testing