Description and Features
Ethernet 200G MAC core is compliant with IEEE Standard 802.3.2018 and IEEE 802.3b Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of lowcost devices. Ethernet 200G MAC IP is proven in FPGA environment. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
Features
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Compliant with IEEE Standard 802.3-2018 specification and IEEE 802.3b specification.
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Supports full duplex mode of operation
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Supports standard 200Gbps Ethernet link layer data
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Supports CDMII (Clause 116) interface.
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Supports 64bit Transmit and Receive Path
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Supports Programmable Inter Packet Gap and Preamble length
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Supports MDIO (Clause 22 and Clause 45) Interface
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Supports start control character alignment
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Provides detailed statistics as per specification
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Supports Jumbo Frame
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Supports Loopback functionality
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Supports transmit and receive FIFO interface
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Supports FCS(CRC) transmission and reception
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Supports Pause frame-based flow control
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Supports IEEE Standard 802.3az Energy Efficient Ethernet (EEE)
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Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
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Supports Wake-on-LAN
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In house UNH compliance tested
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Optional support for TCP/IP
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Optional support for IEEE Standard 1588-2008 PTP
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Optional support for DMA support for both transmit and receive side
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Fully synthesizable
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Static synchronous design
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Positive edge clocking and no internal tri-states
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Scan test ready
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Simple interface allows easy connection to Microprocessor/Microcontroller devices
Benefits
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Single Site license option is provided to companies designing in a single site.
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Multi Sites license option is provided to companies designing in multiple sites.
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Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
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Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs
Deliverables
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Verilog RTL design
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Seamlessly embedding waivers into validation scripts for comprehensive Linting, CDC analysis, and Synthesis coverage
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Provision of detailed and comprehensive reports providing extensive insights into Linting, CDC analysis, and Synthesis methodologies
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Effective utilization of IP-XACT RDL to generate address maps efficiently
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Consolidation of firmware code and Linux drivers into a unified bundle
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Provision of thorough technical documentation covering all aspects comprehensively
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Creation of a Verilog Test Environment integrating intuitive test cases for thorough testing
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Precision crafting of Verilog RTL code with meticulous attention to detail
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Assurance of robustness and reliability in Linting, CDC analysis, and Synthesis through seamlessly integrated QA scripts and waivers
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Delivery of detailed and comprehensive reports meticulously scrutinizing Linting, CDC analysis, and Synthesis processes in significant depth.