Sneak peek into SiFive’s most powerful Risc-V yet

SiFive has briefly pulled back the curtains on its most powerful Risc-V processor yet.

SiFive Next Generation Risc-V core

So far only called ‘Next Generation Core’ or Next-Gen, its official name, final design specs and availability will be unveiled early in December at the Risc-V Summit.

The headline figure is that it will improve on the P550’s performance, currently SiFive’s most powerful processor, by 50%. P550 is benchmarked at 8.7SpecInt2k6/GHz (2.4GHz 7nm 0.23mm2). The company also said it will out-perform Arm’s Cortex-A78 – wait until December to make your own comparison.

SiFive P550 Risc-V coreFrom the diagrams, Next Generation (above right) can now have 16 or more cores executing the Risc-V RV64GBC instruction set, compared with the four allowed in P550 (left), and it has up to three more memory ports, plus up to 16Mbyte of L3 cache instead four. Both have out-of-order execution.

Are these the only differences?

“The SiFive Next-Gen features a quad-issue out-of-order pipeline, as well as other new features we have not yet disclosed,” the company told Electronics Weekly. “The microarchitecture is similar to the P550, which has a triple-issue thirteen-stage design. Additionally, Next-Gen processor architecture will include a network-on-chip suitable for the final scale-out requirement, up to 128 cores.”

Two other technologies will be included for the first time in a SiFive core, branded WorldGuard and Power Dial.

SiFive Power Dial Risc-VPower Dial – SiFive’s presentation labelled this as a P550 graph despite saying Next Gen will be the first to get it.

Power Dial is for power saving and includes dynamic voltage and frequency scaling [DVFS] “as well as other technologies and design methodologies to manage performance and energy use at both idle and dynamic states. Customer applications will be able to control Power Dial to match their needs for the workload and design point”, is all the company would add.

SiFive WorldGuard Risc-VWorldGuard example: world 2 is shared between software context 1 and 2

WorldGuard is a virtualisation technique for hypervisors, isolating physical address regions among software contexts – isolating software contexts using world identifiers. A trusted agent, for example Risc-V M-mode, assigns world identifiers.

One other mooted Next Gen enhancement is improved error detection, recovery, notification and forwarding for safety-critical application where functional safety is a requirement.

Risc-V summit details can be found here


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