The SPI Engine Execution peripheral forms the heart of the SPI Engine framework. It is responsible for handling a SPI Engine control stream and translates it into low-level SPI bus transactions.

Name	Description
spi_engine_execution_1.v	Verilog source for the peripheral.
spi_engine_execution_v1_1_hw.tcl	TCL script to generate Platform Designer IP

Name	Description	Default
NUM_CS	Number of chip-select signals for the SPI bus (min: 1, max: 8)	1
DEFAULT_SPI_CFG	Reset configuration value for the SPI Configuration Register	0
DEFAULT_CLK_DIV	Reset configuration value for the prescaler clock divider register	0
DATA_WIDTH	Data width of the parallel data stream. Will define the transaction's granularity. Supported values: 8/16/24/32	8
NUM_OF_SDI	Number of multiple SDI lines, (min: 1, max: 8)	1

Name	Type	Description
clk	Clock	All other signals are synchronous to this clock.
resetn	Synchronous active-low reset	Resets the internal state machine of the core.
active	Output	Indicates whether the peripheral is currently active and processing commands.
ctrl	SPI Engine Control Interface slave	SPI Engine Control stream that contains commands and data for the execution module.
spi	SPI bus interface master	Low-level SPI bus interface that is controlled by peripheral.

The SPI Engine Execution Module module implements the physical access to the SPI bus. It implements a small but powerful programmable state machine that translates a SPI Engine command stream into low-level SPI bus access.

Communication with a command stream generator happens via the ctrl interface and the low-level SPI access is handled on the spi interface. The active signal is asserted as long as the peripheral is busy executing incoming commands.

Internally, the SPI Engine execution module consists of an instruction decoder that translates the incoming commands into an internal control signal, a multi-function counter and comparison unit that is responsible for handling the timing, and a shift register which holds the received and transmitted SPI data.

The module has an optional programmable pre-scaler register that can be used to divide the external clock to the counter and comparison unit.

Note : The AD463x design uses The SPI Engine Execution Module_1 which is the modified version of SPI Engine Execution. In the SPI Engine Execution Module the sdi data is captured at internal trigger_rs pulse high at clk rising edge. The data capture timing parameter is satisfied for sclk < 50Mhz. For sclk > 50Mhz, in case of AD463x sclk=80Mhz the sdi data is captured at rising edge of sclk and shifted internally in register, also the last sdi bit is captures live in a combinational logic to meet timing parameter. This design modification is controlled by a localparam ONE_BIT_SHIFT defined in SPI Engine Execution Module_1. For details refer HDL file in link above.

SPI Engine

---

Return to AD463x Platform FPGA Architecture

Information on this site was obtained from