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AD463x Platform FPGA Architecture SPI Engine Control Interface

d-samal edited this page Feb 15, 2022 · 1 revision

SPI Engine Control Interface

The SPI Engine Control Interface is used to exchange data between different cores within the SPI Engine framework. It is used to exchange the commands and synchronization points as well as the SPI bus transmit and receive data.

The interface consists of four streams:

  • The CMD stream which carries the SPI Engine commands. (Master to Slave)
  • The SDO stream which carries the transmit data for the SPI bus. (Master to Slave)
  • The SDI stream which carries the received data from the SPI bus. (Slave to Master)
  • The SYNC stream which carries the synchronization events. (Slave to Master)

Each of the streams has a valid, ready and data signal. They follow the handshaking protocol as defined by the AMBA AXI standard. Meaning the master asserts valid when the data on the data signal is valid and the slave asserts ready when it is able to accept new data. If both valid and ready are asserted at the same time the data has been transmitted from the master to the slave.

Files

Name Description
spi_engine_ctrl_rtl.xml Interface definition file

Signal Pins

Name Direction (Master) Description Interface
cmd_ready Input Ready signal of the CMD stream
cmd_valid Output Valid signal of the CMD stream
[15:0] cmd_data Output Data signal of the CMD stream
sdo_ready Input Ready signal of the SDO stream
sdo_valid Output Valid signal of the SDO stream
[DATA_WIDTH-1:0] sdo_data Output Data signal of the SDO stream
sdi_ready Output Ready signal of the SDI stream
sdi_valid Input Valid signal of the SDI stream
[(NUM_OF_SDI*DATA_WIDTH-1):0] sdi_data Input Data signal of the SDI stream
sync_ready Output Ready signal of the SYNC stream
sync_valid Input Valid signal of the SYNC stream
[7:0] sync_data Input Data signal of the sync stream



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