Description and Features
The high-bandwidth applications benefit from the low power, multi-lane, and high-performance PCIe 4.0 PHY IP's design. A full variety of PCIe 4.0 Base applications are supported by the PCIe 4.0 IP, which also complies with the PIPE 4.4.1 specification. The IP integrates high-speed mixed signal circuits to support PCIe 4.0 traffic at 16Gbps. It is backward compatible with data rates of 2.5Gbps, 5.0Gbps, and 8.0Gbps for PCIe 3.1, PCIe 2.1, and PCIe 1.1, respectively. The PCIe 4.0 IP may satisfy the needs for various channel circumstances since it supports both TX and RX equalisation methods.
Features
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Compliant with PCIe 4.0 Base Specification
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Compliant with PIPE 4.4
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Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
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Supported physical lane width: x4
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Supported parallel interface: 32-bit
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Supported input reference clock: 100 MHz
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Supported parallel interface data clock: 62.5 MHz, 125 MHz and 250 MHz and 500MHz
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Supporting low power operation with configurable setting in power state P1/P2/L1 PM Substates: PLL control, reference clock control, and embedded power gating control
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Silicon proven in TSMC 7nm
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Operating Voltage: 0.8V and 1.2V
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Providing robust testability by low-cost Build-In Self-Test (BIST) via near-end analog and external loopback interface as well as far-end analog/digital loopback interface
Deliverables
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GDSII & layer map
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Place-Route views (.LEF)
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Liberty library (.lib)
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Verilog behaviour model
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Netlist & SDF timing
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Layout guidelines, application notes
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LVS/DRC verification reports
