RISC-V Overview10%

History of RISC-V: The Free and Open ISA
RISC-V International
RISC-V Documentation
Contribute to RISC-V

RISC-V Instruction Set Architecture35%

RV32I and RV64I
Understand Instruction Formats: branching, accessing memory, and accessing data structures
Understand the modularity of RISC-V as an ISA: core ratified (M, C, F, D, A) and other extensions
Understand Privilege Modes, system calls, CSRs, exceptions, and interrupt handling
Understand memory model, cache management, and virtual memory management

Assembly Language for RISC-V25%

Understand RISC-V specific assembly language syntax and features, including CSR access
Write and debug RISC-V assembly code
Assess performance of assembly code
Convert high-level code to assembly code

High Level Languages for RISC-V: C Programming15%

Understand RISC-V tools including compilers, debuggers, simulators, performance tools, OSes, and SDKs
Understand calling conventions (ABIs), the stack, and disassembly
Understand inline assembly

RISC-V Operating Systems & Tools15%

Fundamentals of Operating Systems including implementing basic OS functionality in RISC-V ASM
Understanding basic use and functionality of firmware for RISC-V platforms
Understanding microcontrollers versus application processors
Running RISC-V Applications in a General Purpose OS

RISC-V Foundational Associate (RVFA)

Stay Up to Date