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intoPIX offers various possibilities to assess the JPEG XS technology, our IP-cores and accelerated software libraries. 

Our team has a large experience to support customers to speed-up their integration into a fully functional system. 

​Try our Reference Software and SDKs

Get access the TicoXS reference software executables featuring all JPEG XS profile with intoPIX high quality encoding. This reference software exceeds the quality of the baseline JPEG XS reference software and enable you to assess the compression efficiency.


Get access directly to a trial version of the intoPIX FastTicoXS SDKs for CPU or GPU . 

This commercial libraries are highly optimized in speed to meet both the highest requirements in terms of high pixel rates and extremely low latency. Moreover the SDKs have been integrated with third party libraries such as the Nvidia Rivermax SDK for SMPTE 2110, FFmpeg, etc..

​Try our FPGA Development Kits

intoPIX accelerates customer product developments with video application reference designs / proofs of concept. The reference designs aim to deliver a powerful proof of concept using intoPIX’s high-performance TicoXS IP-cores. 


We deliver reference designs for both Intel & AMD-Xilinx FPGAs. 

​Compact HDMI2.0 4K example design on Intel Cyclone 10 or Arria 10 FPGA 

 In collaboration with  Intel, intoPIX offers an evaluation design of this standard on an Intel® Cyclone® 10 GX or Arria® 10 SoC Development Kit: an easy way to test and implement JPEG XS profile or intoPIX Flawless Imaging profile for your embedded video and image processing application.

The example design targets the Intel® Cyclone® 10 GX or Arria® 10 SoC FPGA Development Kit. Based on Intel HDMI loop-back example design, it uses HDMI 2.0 Video input/output accessible using a mezzanine HDMI daughter card connected to the Development kit via an FMC connector. A JPEG XS 4K 60fps  Encoder - Decoder chain is introduced between the Intel HDMI 2.0 IP-Cores using the TicoXS IP-cores, with a JTAG connection allowing the user to adjust the compression ratio of the intoPIX codec. The Arria 10 Soc design features also the Flawless Imaging profile on top of the JPEG XS High profile

4K60 HDMI Encoding -Decoding Loopback on Intel FPGA Demonstration Platform

Features 

  • Easy evaluation intoPIX codecs quality, latency, at various compression ratios using a real-time encode-decode loop-back.
    • On Cyclone 10 Dev Kit , TicoXS encoder/decoder (JPEG XS High profile)  up to UHD4K 60 frames per second (fps) 444/422
    • On Arria 10 Dev Kit , TicoXS FIP encoder/decoder (JPEG XS High profile with Flawless Imaging profile ) and up to UHD4K 60 frames per second (fps) 444/422
  • Compact implementation suitable for edge-centric FPGAs .
  • Configurable codec settings allow you to evaluate different bandwidth and compression ratios.

Benefits 

  • Easy way to evaluate intoPIX IPs in FPGA, requiring only a single Intel Cyclone® 10 GX or Arria® 10 SoC Development Kit + one HDMI 2.0 FMC daughter card. 
  • Full Intel end-to-end solution: use the same video codec in your embedded FPGA design with the intoPIX hardware IP and in your CPU design with the intoPIX software development kit (SDK).


​Compact HDMI 2.0 4K & HDMI 2.1 8K example designs on Intel Cyclone 10, Arria 10 or Agilex 7 FPGAs

In collaboration with  Intel, intoPIX offers an evaluation design of this standard on an Intel® Cyclone® 10 GX, Arria® 10 or Agilex® 7 FPGA SoC Development Kit: an easy way to test and implement JPEG XS profile or intoPIX Flawless Imaging profile for your embedded video and image processing application.

The example design targets the Intel® Cyclone® 10 GX or Arria® 10 SoC FPGA Development Kit. Based on Intel HDMI loop-back example design, it uses HDMI 2.0 Video input/output accessible using a mezzanine HDMI daughter card connected to the Development kit via an FMC connector. A JPEG XS 4K 60fps  Encoder - Decoder chain is introduced between the Intel HDMI 2.0 IP-Cores using the TicoXS IP-cores, with a JTAG connection allowing the user to adjust the compression ratio of the intoPIX codec. The Arria 10 Soc design features also the Flawless Imaging profile on top of the JPEG XS High profile

4K60 HDMI Encoding -Decoding Loopback on Intel FPGA Demonstration Platform

The example design targets the Intel® Agilex® 7 SoC FPGA Development Kit. Based on Intel HDMI loop-back example design, it uses HDMI 2.1 Video input/output accessible using a mezzanine HDMI daughter card connected to the Development kit via an FMC connector. A JPEG XS 8K 60fps  Encoder - Decoder chain is introduced between the Intel HDMI 2.1 IP Cores using the TicoXS IP cores, with a JTAG connection allowing the user to adjust the compression ratio of the intoPIX codec. The Agilex Soc design features also the Flawless Imaging profile on top of the JPEG XS HIGH profile and JPEG XS TDC profile.

Features 

  • Easy evaluation intoPIX codecs quality, latency, at various compression ratios using a real-time encode-decode loop-back.
    • On Cyclone 10 FPGA Dev Kit , TicoXS encoder/decoder (JPEG XS High profile)  up to UHD4K 60 frames per second (fps) 444/422
    • On Arria 10 FPGA Dev Kit , TicoXS FIP encoder/decoder (JPEG XS High profile with Flawless Imaging profile ) and up to UHD4K 60 frames per second (fps) 444/422
    • On Agilex 7 FPGA Dev Kit, TicoXS encoder/decoder (JPEG XS HIGH & TDC Profiles) up to UHD8K 60 frames per second (fps) 444/422/420
  • Compact implementation suitable for edge-centric FPGAs .
  • Configurable codec settings allow you to evaluate different bandwidth and compression ratios.

Benefits 

  • Easy way to evaluate intoPIX IPs in FPGA, requiring only a single Intel Cyclone® 10 GX or Arria® 10 SoC Development Kit + one HDMI 2.0  FMC daughter card.
  • Requires only an Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile) and HDMI 2.1 FMC daughter card: one board implements an encode-decode loopback.
  • Full Intel end-to-end solution: use the same video codec in your embedded FPGA design with the intoPIX hardware IP and in your CPU design with the intoPIX software development kit (SDK).


​4K SMPTE 2110-22 low latency over IP example design on AMD-Xilinx ZCU106 FPGA with TicoXS or TicoXS FIP encoder/decoder cores

This advanced design supports the transport of a compressed Video stream over an IP network, taking you closer to a typical Broadcast or ProAV use case and showing the full benefit of a compressed workflow.

Using the AMD-Xilinx ZCU106 development kits and their integrated HDMI 2.0 connectors, a "sender" design receives your 4K60 Video input, performs a JPEG XS compression followed by a SMPTE 2110-22 compliant RTP mapping, to be transported as an independent RTP essence over a Gigabit-Ethernet (1GBE) and 10-Gbps Ethernet (10GbE) network via the board sfp connectors. A matching "receiver" design on a similar ZCU106 will handle the mirroring operation, with an RTP depacketizer, JPEG XS decoder and HDMI Video output. 
The same example design also enables to evaluate the Flawless Imaging Processing (FIP) featured in the TicoXS FIP cores for advanced compression efficiency of screen content.
4K60 HDMI over IP design on AMD-Xilinx FPGA Demonstration Platform

Features 

    • Evaluation of a complete compressed video transport stream,  at various compression ratios using separate sender and receiver designs.
    • Compact implementation suitable for edge-centric FPGAs with no need for external DDR memory for the compression scheme.
    • Xilinx (AMD) HDMI 2.0 TX and RX subsystems.
    • IntoPIX TicoXS IP-cores up to UHD4K 60 frames per second (fps) 444/422 encoder and decoder IP-cores for JPEG XS High profile.
    • IntoPIX TicoXS FIP IP-cores up to UHD4K 60 frames per second (fps) 444/422 encoder and decoder IP-cores for JPEG XS High profile with Flawless Imaging profile.
    • intoPIX TicoXS RTP payload IP-cores as defined in SMPTE ST2110-22, used for independent RTP essence transport as recommended by VSF TR08.
    • Xilinx (AMD) Ethernet with either 10GBE or 1GBE RX & TX SubSystems.
    • Configurable codec settings allow you to evaluate different bandwidth and compression ratios.

    Benefits 

    • A starting point to evaluate actual Low latency compressed video Transport over a compliant SMPTE 2110-22 IP network,  requiring just two Xilinx (AMD) ZCU106 Development Kits & appropriate SFPs.
    • Encoder/Decoder and RTP IP-cores by intoPIX completly integrated into the Xilinx (AMD) framework.

    ​Support & Customization Services

    With responsiveness, anticipation and availability, intoPIX offers support services around the integration of its IP-cores and SDKs. These services are well-suited for the life cycle of any type of audio-visual system. intoPIX helps you to accelerate your time to market and to define the most suitable solutions for your applications.

    intoPIX development support guarantees:

    • A nominative contact that ensures the continuity of your relationship with intoPIX
    • Specific awareness of your environment, equipment details and technical case history
    • Access to our technical experts. This allows you to get quick answers to any of your technical questions
    • Update and upgrade notifications and support
    • Interoperability. intoPIX will make sure that your system is in line with current standards

    In addition to the inherent flexibility of our IP cores and SDKs, we understand that some applications may include special requirements that are outside the scope of standard integration support. intoPIX can help tailor standard IP blocks  and software to meet specific needs where required. Please CONTACT US for more information about our customization services.