Description and Features
The Hardware Encoder Video Accelerator (HEVA), supports HEVC encoding low complexity with a flexible architecture targeting at least 1080p60 with minimal processing units and memory cuts and up to 2160p120 with large number of units and large memory cuts. Trade-off performance/area at design configuration: Reference cache size for 2160p30 at 350 MHz, 1 reference frame and bandwidth, overhead of 100% for references i.e. 1.5 GBytes/sec (minimal is 1.2 GB/s) Hardware interfaces :Host interface AXI3/AXI4 slave interface for the registers and command/status FIFO, Memory interface AXI3/AXI4 Streaming interfaces to External DRAM, Asynchronous AXI3/AXI4 128 bits interface, Synchronous DMA arbiter and memory interface Task sequencing modules: Manages communication and storage between processing modules, Control the shared memories and caches between the TPU modules and TSU/MIF, Defines the execution mode of the task processing units Task processing modules: Perform the pixel and bit-stream processing under control of TCR/TSU, The number of processing elements is defined at design configuration to sustain the required performance, A local reference cache is needed for performance for some processing units.
Features
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Encoder acceleration
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Performance up to 330 Mpixel/sec (2160p30 + 1080p30)
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HEVC Main support, Level 4.2 (2160p30)
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H.264 High Profile Progressive, Level 5.1 (2160p30, 1080p120)
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HEVC Sample Adaptive Offset in-loop deblocking
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Full coding unit support (from CU 64x64 to CU 8x8, PU 4x4)
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No restriction on MV range allowed (X<8192, Y<4096)
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Slice support: single slice or number of CTB lines per slice
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Slice level IT programmable
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Original input frame
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Bottom/Right original padding on-the-fly
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YUV 420 semi-planar: NV21
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Reference frame usage
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Internal 2D frame format
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Optional proprietary lossless compression on reconstructed/reference frames
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Up to two reference frames
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Generalized P/B frames for low delay encoding
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GOP up to 8 frames hierarchical B-frames for random access encoding
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Motion vector range not limited, trade-off bandwidth versus MV range up to the application programming and design configuration.
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Programmable quality/performance trade-off
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Optional user defined input parameters
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Deblocking slice parameters
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User defined quantization scaling matrix tables
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Chroma QP offsets
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Region of interest input map table
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Motion vector of Interest input map table
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Optional user report output
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Motion vector field
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with/without Basic picture analysis
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Latency tolerance at design configuration
Deliverables
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RTL Source Code
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HDL based test bench and behavioral models
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Test cases
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Protocol checkers, bus watchers and performance monitors
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Configurable synthesis shell
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Documentation & Design Guide
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Verification Guide
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Synthesis Guide
Applications
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HEVC & H264 Recorder & Transcoder, for NAS application for Set Top Box application Best in Class HEVC Transcoder .
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HEVC & H264 Video monitoring on video surveillance sequences –
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On outdoor, non-static sequences ~5 to ~10% of bit-rate reduction
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On outdoor, static sequences ~10 to 20% of bit-rate reduction
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On indoor & lowlight sequences ~10% of bit-rate reduction
