By: Marvin Denman, NVIDIA, and Francisco Socal, Arm
Acknowledgments: Jonathon Evans, NVIDIA, Vikram Sethi, NVIDIA, Swadesh Choudhary, Intel, Bruce Mathewson, Arm, Phanindra Mannava, Arm, and Durgesh Srivastava, NVIDIA
During the annual Flash Memory Summit last week, UCIe announced the release of its new 1.1 Specification. This was important news for developers interested in advancing streaming protocols, and, in particular, the AMBA® Coherent Hub Interface (AMBA CHI).
AMBA CHI provides the performance and scale required for systems with a very large network of processors, accelerators, and memory. Developed by Arm in collaboration with various industry partners to enable designs that require coherency between multiple devices, it is designed for scalability to build small, medium, or large systems. It has flexibility to support ring, mesh, and crossbar topologies and has been established as an industry standard within the Arm ecosystem and beyond. Expanding it to support chiplet connections allows for coherence between chiplets that use AMBA CHI as their coherence mechanism.
UCIe Specification 1.0 was released in 2022 and specifically addressed communication of PCIe and CXL protocols between chiplets, providing Raw Mode for streaming protocols. Raw Mode bypasses many of the functions of UCIe, including error detection and replay, leaving it up to the implementer to provide a mechanism for data reliability as needed. Many potential usages of UCIe will employ a protocol other than PCIe/CXL but prefer the UCIe infrastructure provided for PCIe/CXL. The UCIe 1.1 Specification enables the use of these other protocols to provide reliable data and allows for streaming protocols to reuse the existing logic in UCIe for error detection and replay.
The AMBA CHI protocol has many of the same reliability requirements as PCIe/CXL. Using Raw Mode streaming for CHI protocol requires developing implementation-dependent error detection and correction mechanisms. Not including these mechanisms as part of a standard could result in increased fragmentation of the market and incompatibility between chiplets that use UCIe to communicate CHI protocol. CHI will be specifying a standardized method for packing the CHI protocol into UCIe-compatible flits. Using UCIe streaming flits (a 1.1 Specification enhancement) for these packed flits provides standardization on the means of chiplet communication of the CHI protocol over a highly reliable connection.
UCIe support for streaming flits allows other protocol messages to be mapped into the payload portion of flits that are compatible with PCIe and CXL flit types already supported by UCIe. The flit type is negotiated during initialization of the UCIe link, with the streaming flit format providing 236 or 250 bytes of payload for CHI packed flits. As with the functions provided to both PCIe and CXL, the UCIe Die-to-Die (D2D) adapter inserts flit headers and cyclic redundancy check (CRC) information into the flits, as well as CRC detection and replay mechanisms.
In summary, the UCIe 1.1 Specification provides a compatible method for connecting chiplets and can reliably communicate protocols such as PCIe, CXL, CHI, and many others between chiplets. In addition, UCIe 1.1 can use Raw Mode for communication that does not fall into a protocol. Chiplet vendors and manufacturers can now provide chiplets that meet the UCIe standard, ensuring their interoperability.
Download the UCIe 1.1 Specification today, and join our industry leading Consortium members as they continue to grow the chiplet ecosystem.
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