D&R News Alert
June 12th, 2025


Welcome to the issue of June 12th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Design platform and Services
■ FAMES Pilot Line Launches FAMES Academy To Train Europe’s Chip Engineers with Skills to Leverage FD-SOI Technology and Design Circuits Using Advanced Setups
More about FD-SOI
■ Cadence Advances Design and Engineering for Europe's Manufacturers on NVIDIA Industrial AI Cloud
■ sureCore launches comprehensive suite of silicon services for next generation devices
True Circuits
  • Low-jitter, pin-programmable PLL and DLL hard macros
  • High-performance, general purpose and easy-to-integrate
  • TSMC, UMC and GF processes from 180nm to 4nm
TSMC 7nm CG H PLL >> Learn more >>

Chiplets
■ Qualitas Semiconductor Successfully Develops UCIe v2.0-Compliant PHY IP, Enabling Up to 512Gbps Die-to-Die Connectivity
Analog IP
■ Imec presents 150 GSa/s Digital-to-Analog Converter (DAC) achieving 300 Gb/s data transmission
Memory Subsystems
■ OPENEDGES Collaborates with Renesas on Memory Subsystem IPs for Next-Generation MPU Platform Development
■ CFX's 130nm EEPROM IP Passes Customer Product-Level Evaluation, Ready for Mass Commercial Adoption
■ Numem Addresses AI's Dirty Secret: Memory Is the Real Bottleneck
■ Faraday Unveils FlashKit™-22RRAM: an eNVM-based SoC Development Platform for IoT
■ Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions - by Innosilicon
Xiphera
nQrux® Crypto Module
• Customisable security platform
• Robust encryption & hashing
• Quantum-safe crypto option
• Pure RTL with no hidden CPU/software
 Learn more >>
Meet us – FPGA Conference in Munich, July 1–3!

Interface IP
■ Synopsys Achieves PCIe 6.x Interoperability Milestone with Broadcom's PEX90000 Series Switch at PCI-SIG DevCon 2025
■ PCI-SIG® Announces PCIe® Optical Interconnect Solution
RISC-V
■ Andes Technology Announces AndeSight™ IDE v5.4 to Streamline AI and Embedded Software Development on RISC-V 
■ IAR Platform Accelerates Embedded Development with Updated Toolchains for Arm and RISC-V
Artificial Intelligence
■ Elliptic Labs' AI Platform Now Optimized for Ceva's NeuPro-Nano NPU - Enabling Smarter Edge Devices
■ VeriSilicon's AI-ISP Custom Chip Solution Enables Mass Production of Customer's Smartphones 
■ Rambus at Rosenblatt’s AI Summit: Navigating Memory in AI’s Future
■ UK plans $1bn AI supercomputer
Worried About Insider Threats? Start with PUF

PUF Security + Ememory
• Powered by NeoPUF, generates unconable UID and root key on-chip
• Combines OTP, TRNG, and protections to form a Root of Trust
• Flexible integration with Crypto Engine and HSM, from IoT to Edge
• PQC-ready to tackle AI and quantum security threats
PUFsecurity Product Portfolio

Communication
■ IP Cores, Inc. ships new FFT4T Streaming Multi-Channel FFT Core
Automotive
■ Siemens’ PAVE360 to support Arm Zena Compute Subsystems
Security solutions
■ NCSC proposes its PQC transition timeline to UK Policy makers: guiding the UK to a quantum-safe future, Jeremy Bradley NCSC- podcast from PQshield
Multimedia
■ IntoPIX Presents Its New Titanium Software Suite: Empowering AV-Over-IP Workflows With Speed, Quality & Interoperability
■ Silicon Proven DisplayPort 1.4 Tx & Rx PHY IP Cores, Ready to license in 12/28/40/55nm
Green Electronics
■ Transition Plan: Leonardo publishes its transition strategy
Partner News
■ BOS Semiconductors, Selected for the 2025 Innovation Premier 1000
■ Joseph von Fraunhofer Prize 2025 for research team at Fraunhofer IIS
Business News
■ TSMC May 2025 Revenue Report
■ Samsung’s Gap with China’s SMIC in Foundry Market Narrows to Mere 1.7%





Chips'n media
WAVE-N : Specialized video processing NPU

• Fully Programmable Processing Core
• Extreme Efficiency for Modern CNN Computation such as SR, NR and Demosaic.
• Highly optimized for 4K real-time video processing
• 1024 16bit floating point MACs and minimum DRAM bandwidth consumption

 >> more about WAVE-N

What they said at
IP SoC Silicon Valley 25

Professional videography ecosystem and APV CODEC
Andy Lee, Vice president, US marketing, Chips&Media, Inc.

The Role and Importance of Interface IP in On-Device AI Semiconductor Design
Pyungsu Han, PhD, VP/ CTO, Qualitas Semiconductor

MIPI (Mobile Industry Processor Interface): Central Nervous System of Automotive Industries
Snigdha Dua,Tejaswari V, Manager,Staff, Synopsys, Inc.

USB4 - Advanced USB Interface for broad market
Hiral Patadiya, Sr. Tech Manager, System Level Solutions, Inc.

Power Management Sensors and LDO for Datacenter, AI and Chiplets
Rolly Baradiya, Circuit Design Engineer, Analog Bits Inc.

Architectures and IP for SoC Clocking
Jeff Galloway, Principal/ Co-Founder, Silicon Creations

Efficient by Design: Revolutionizing Power Management in SoCs
Floriberto Lima, CEO, SiliconGate

Cost-effective AI MCU featuring a standard logic compatible embedded flash memory
Peter Song, CEO and Co-Founder, ANAFLASH Inc.

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