Welcome to the issue of June 16th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.
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Rambus Federal Webinar Series
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- Join us for our webinar series: Mission: Secure – Safeguarding Government Systems from Silicon to Software
- Weekly webinars on cutting-edge hardware security solutions for government
- Topics: Tamper-resistant security, defense-grade Root of Trust, MACsec, Quantum Safe Cryptography and more
- Starting June 17th, every Tuesday
Register Today >>
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- Low-jitter, pin-programmable PLL and DLL hard macros
- High-performance, general purpose and easy-to-integrate
- TSMC, UMC and GF processes from 180nm to 4nm
TSMC 7nm CG H PLL >>
Learn more >>
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AI data compression option on VPX cores
• ARC processors are optimized to deliver the best PPA efficiency in the industry for embedded SoCs
• Harvard architecture for higher performance through simultaneous instruction and data memory access
What they said at
IP SoC Silicon Valley 25
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How do you select the right memory architecture and choose between LPDDR, GDDR, and HBM?
Dirk Seidel, Marketing Director, Innosilicon
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Building Tomorrow Today: Innovating with IP
Ook Kim, CEO, 4lynx, Inc.
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makeChip: an accessible, cost-effective, and cloud-based Chip Design Platform
Florian Bilstein, Director Design Service, Racyics GmbH
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Challenges of Porting ASIC IP Cores to FPGA: Tricky but Worthwhile!
Ettore Giliberti, Senior Staff Application Engineer, SmartDV Technologies
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