D&R News Alert
July 10th, 2025


Welcome to the issue of July 10th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Technology News
■ 18nm FDSOI with ePCM... a technology for edge AI - By Dominique THOMAS, Director, Funded Programs France
Foundry News
■ Samsung Targets 70% 2nm Yield in 6 Months to Win Big Clients
■ Infineon to Start 300 mm GaN Wafer Production as TSMC Exits Market
■ GlobalFoundries to Acquire MIPS to Accelerate AI and Compute Capabilities
NeoFuse OTP Qualifies on TSMC N3P Process, Securing the Future of AI & HPC

• Meet the demands of AI and HPC SoCs, handling next-gen design complexity
• High-density OTP (up to 4Kx40) with wide voltage range (0.55–0.96V)
• Built-in NeoPUF security for TRNG, Secure Boot, and Root of Trust
• System-level wrapper design with verified APB and MBIST interfaces

 		PUF Security + Ememory


Read More >>


Design Platform
■ A Deep Dive into AI-Driven Optimization with WiCkeD: The Optimization Powerhouse - By Cadence
■ Custom ASIC Design for CGM, TPMS & SATCOM applications from T2M-IP
■ Lossless Data Compression Webinar: Choosing Algorithms and IP Core Accelerators
Memory interface IP
■ Cadence Introduces Industry-First LPDDR6/5X 14.4Gbps Memory IP to Power Next-Generation AI Infrastructure
RISC-V
■ Andes Technology’ s AutoOpTune™ Applies Genetic Algorithms to Accelerate RISC-V Software Optimization
■ Andes Technology Advances High-Performance RISC-V Strategy with U.S.-based Design Center: Condor Computing
■ 160-core RISC V Board Is The M.2 CoProcessor You Didn’t Know You Needed
Mutli processor SoC
■ SiPearl finally tapes out Europe’s supercomputer chip
Security
■ PUFsecurity, a subsidiary of eMemory, Achieves NIST CAVP Certification for PQC Algorithms, Launches PUFpqc Architecture for Quantum-Resilient SoCs
Rambus
Rambus Federal Webinar Series
  • Join us for our webinar series: Mission: Secure – Safeguarding Government Systems from Silicon to Software
  • Weekly webinars on cutting-edge hardware security solutions for government
  • Topics: Tamper-resistant security, defense-grade Root of Trust, MACsec, Quantum Safe Cryptography and more
  • Starting June 17th, every Tuesday
 Register Today >>

Artificial Intelligence
■ French Startup Combines Electronics, Photonics And Optics For AI
■ OpenAI scales security to protect IP from Chinese foreign espionage threats
■ 3 Acquisitions Show Heavy Investment in AI, IoT, and High-End Processors
Partner News
■ Scaling for Success: How Weebit is Preparing for its Next Phase of Growth
Business News
■ A statement from Tony Hemmelgarn
■ Europe prepares its Quantum Act
■ Exclusive: Arm estimates a 14-fold increase in data center customers since 2021, company says





New IP
• FH-OFDM Modem by Global IP Core Sales
• Chimera QC Multi 864 TOPS general purpose NPU by Quadric
• LVDS I/O Buffer 40/28/22/16/7nm by Renesas

What they said at
IP SoC Silicon Valley 25

USB4 - Advanced USB Interface for broad market
Hiral Patadiya, Sr. Tech Manager, System Level Solutions, Inc.

Power Management Sensors and LDO for Datacenter, AI and Chiplets
Rolly Baradiya, Circuit Design Engineer, Analog Bits Inc.

Architectures and IP for SoC Clocking
Jeff Galloway, Principal/ Co-Founder, Silicon Creations

Efficient by Design: Revolutionizing Power Management in SoCs
Floriberto Lima, CEO, SiliconGate

Cost-effective AI MCU featuring a standard logic compatible embedded flash memory
Peter Song, CEO and Co-Founder, ANAFLASH Inc.

How do you select the right memory architecture and choose between LPDDR, GDDR, and HBM?
Dirk Seidel, Marketing Director, Innosilicon

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