D&R News Alert
July 14th, 2025


Welcome to the issue of July 14th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Foundry Ecosystem News
■ Japanese Semiconductor Manufacturer Races Toward 2nm, Backed by IBM
■ IC’Alps Joins GlobalFoundries GlobalSolutions™ Ecosystem to Accelerate ASIC Development
Design Platform
■ Introducing Cadence's Virtuoso Studio RF: Advancing RF Design for 3D-IC - by Cadence Design Systems
■ Wavetek Deploys Silvaco’s Victory TCAD™ to Drive Innovation in GaN-Based Connectivity Solutions
Memory Interface Standards
■ JEDEC® Releases New LPDDR6 Standard to Enhance Mobile and AI Memory Performance
Webinar - Unpacking System Performance:
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Interface IP
■ Arasan Announces immediate availability of its Total IP for Embedded USB2 (eUSB2) with Controller and PHY
HPC Processor
■ Europe's first HPC ARM processor lands at TSMC
RISC-V
■ RISC-V Solidifies Presence in China as Global Momentum Builds
Automotive
■ From smarter sensing to safer driving: GlobalFoundries solutions driving ADAS innovation
■ Keysight and Korea Automotive Technology Institute Team Up to Improve Vehicle-to-Everything Component Testing
■ The Role of Data Annotation in Building Autonomous Vehicles - By Moschip
Aerospace Communication
■ IPrium releases SOQPSK-TG Demodulator for Aerospace Telemetry
Audio IP
■ Tech Note: Use this Flexible and Efficient AC’97 IP Core for Simple Audio Interfaces and Legacy System Upgrades
Partner News
■ First Tetrivis LTD Consumer Product is Finalist in IEEE Smart Lighting "Let's Make Light" Contest.
■ Ceva, Inc. Schedules Second Quarter 2025 Earnings Release and Conference Call
■ TSMC June 2025 Revenue Report
Business News
■ Samsung’s Q2 profit falls short as chip slump, tariffs take toll






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What they said at
IP SoC Silicon Valley 25

Building Tomorrow Today: Innovating with IP
Ook Kim, CEO, 4lynx, Inc.

makeChip: an accessible, cost-effective, and cloud-based Chip Design Platform
Florian Bilstein, Director Design Service, Racyics GmbH

Challenges of Porting ASIC IP Cores to FPGA: Tricky but Worthwhile!
Ettore Giliberti, Senior Staff Application Engineer, SmartDV Technologies

DFT Ready in RTL Level with SOC Canvas
Ahchan Kim, CTO, ITDA Semiconductor Co., Ltd.

PVT Monitors fulfilling the desire for increasing levels of control in Advanced nodes for complete Silicon Lifecycle management in SoCs
Rohan Bhatnagar, Product Manager, Synopsys, Inc.

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