D&R News Alert
August 11th, 2025


Welcome to the issue of August 11th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Rambus
MACsec IP for Automotive
• SO 26262 ASIL-B/D compliant MACsec engine for 10M to 50G Ethernet with TSN support
• Low-latency operation across xMII interfaces including RMII, MII, GMII, and optional XGMII.
• IEEE 802.1AE-2018 compliant with VLAN-in-clear, Cisco ClearTags, and FIPS 140-3 validation.
• Highly configurable for optimal area, throughput and features trade-off
 Learn More >>

Foundry News
■ GlobalFoundries Expands Partnership with Apple to Advance Wireless Connectivity and Power Management, Reinforcing U.S. Chip Manufacturing Leadership
■ Cyient Semiconductors Enters Strategic Channel Partnership with GlobalFoundries
Chiplets
■ UCIe 3.0 Is Here: Synopsys IP Solutions Are Ready
■ UCIe 3.0 Doubles Data Rate For 2D Chiplets
Memory IP
■ CFX Achieves Major Breakthrough in 40nm SONOS Embedded eFlash IP
Attopsemi Ultra-Low Power IP Solutions
on GF 22nm 4k x 8 high density
• Ultra-Small Footprint (0.0166mm^2)
• Low Program Volt 1.6 V ± 5%
• Low Reead Current (0.1 mA)
• Low-Voltage Operation (0.59–0.715 V) on 0.8 V MOS Devices

Learn more >>

Interface IP
■ Arasan Announces the industries first MIPI SWI3S Manager IP and Peripheral Controller IP
RISC-V
■ NVIDIA on RVA23:“We Wouldn’t Have Considered Porting CUDA to RISC-V Without It
■ Linus Torvalds Rejects RISC-V Changes For Linux 6.17
■ 7 Critical Components of the Car of Tomorrow
Artificial Intelligence
■ Open Compute Project Enables Silicon Diversity in AI Clusters
■ ALi Corporation and Ceva Announce Strategic Collaboration to Bring Scalable Edge AI to Next-Gen Video Platforms
Audio
■ Breaking the Silence: What Is SoundWire-I3S and Why It Matters
Space Applications
■ Teledyne e2v Unveils 16GB Radiation-Tolerant DDR4 Engineering Models for Space Applications
■ Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions
Security
■ Silicon Labs Secures Industry First with PSA Level 4 Certification for SiXG301 SoC
Internet of Things
■ AIoT 2.0 brings smarter voice and visual features to connected devices
■ Eseye: Why the true cost of IoT connectivity is often hidden
Partner News
■ Aion Silicon Successfully Completes ISO 9001 and ISO/IEC 27001 Surveillance Audit, Strengthening Commitment to Quality and Security






Synopsys PUF Base
• Proven and mature PUF solution and world’s first IP to be awarded “PSA Certified Level 3...
• Uses standard SRAM power-up values as a PUF and is quantum safe

New IP
• True Random Number Generator IP Block by Crypto Quantique
• LPDDR5x/5 SystemC TLM Cycle Accurate Model by MEMTECH
• IPT LOW POWER UCIE-A PHY by InPsytech
• DDR5 CKD 01 - Clock Driver by MAXVY

What they said at
IP SoC Silicon Valley 25

DFT Ready in RTL Level with SOC Canvas
Ahchan Kim, CTO, ITDA Semiconductor Co., Ltd.

PVT Monitors fulfilling the desire for increasing levels of control in Advanced nodes for complete Silicon Lifecycle management in SoCs
Rohan Bhatnagar, Product Manager, Synopsys, Inc.

Securing Devices/embedded Systems Lifecycle management
Karthik Raj Shekar, Field Application Engineer presales & Junior Project Manager, Secure-IC

Interview with Justin Endo - Director, Marketing & Sales - Mixel, Inc.

REGISTER:
If this newsletter was forwarded to you by a colleague, you can have it sent directly to you at no cost. To register for D&R SoC News Alert, go to:

UPDATE YOUR PROFILE / UNSUBSCRIBE :
You are subscribed as and you receive this Alert in html format.

* If you wish to unsubscribe, you can do it there: