D&R News Alert
September 8th, 2025


Welcome to the issue of September 8th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Rambus
Rambus Design Summit: Memory Solutions for Next-Generation Intelligent Systems
• Join us virtually on October 8th for a morning of sessions exploring AI
• Explore the impact of memory and interconnect technologies on AI performance, scalability, and efficiency across data centers and edge devices
• Dive into the latest memory IP standards like HBM4, LPDDR5, GDDR7, PCIe 7, and CXL 3 that drive next-gen AI
• Hear expert talks on AI’s impact on memory design, demand, and innovation.
 Save Your Seat >>

Foundry News
■ Rapidus 2HP 2 nm Node to Match TSMC N2 on Logic Density
■ Synopsys and GlobalFoundries Establish Pilot Program to Bring Chip Design and Manufacturing to University Classrooms
■ RFSOI, the key to addressing the challenges of cellular RF front-ends
Design Platform
■ Data Patterns (India) Ltd. connects design to manufacturing with software from Siemens Xcelerator
■ Comcores Launches OmniGate: A Versatile and Compact Hardware Evaluation Platform for TSN Ethernet End Stations, Switches, and Gateways
Memory Subystems
■ Gen 5 NVMe Host IP on AGILEX 7 R-Tile!
■ Boost SoC Flexibility: 4 Design Tips for Memory Subsystems with Combo DDR3/4 Interfaces by Key ASIC
CEVA Join us at the 2025 Ceva Technology Symposium!
Explore the future of connected intelligence with innovations in:
• Connect – Bluetooth HDT, Wi-Fi 7, UWB 4.0, 5G/6G & Satellite Comm
• Sense – Perception for wearables, robotics & autonomous systems
• Infer – Smarter and faster AI at the Edge & in the Cloud
Herzliya | Shanghai | Hsinchu
Register here >>>

Interface IP
■ SignatureIP Achieves PCI-SIG® PCIe® 5.0 Certification, Joining Elite Group on Official Integrators List
■ New MIPI I/O Bridges Working Group – A Conversation with Chair Aruni Nelson
Artificial Intelligence
■ Synopsys Announces Expanding AI Capabilities for its Leading EDA Solutions
■ Cadence to Acquire Hexagon’s Design & Engineering Business, Accelerating Expansion in Physical AI and System Design and Analysis
■ BrainChip’s Cloud Platform Lets Developers Use Its Neuromorphic Tech
Security and Safety
■ Siemens Joins the CHERI Alliance: a United Front for Cutting-Edge Cybersecurity
■ Xiphera Builds Faster and More Secure Data Processing – Business Finland Supports Development
■ GPS-Buddy RFID-Tag and ST’s LIS2DUX12: Let’s talk about the new era of tracking assets and safety monitoring
■ Custom hardware helps deliver safety and security for electric traction
Multimedia IP
■ Leader And IntoPIX Boost IP Stream Monitoring With JPEG XS Integration
Wireline Communication
■ Global IP Core Announces the Availability of the NavIC LDPC/BCH Decoder FEC IP for Immediate Integration
Green Electronics
■ GENESIS: Rethinking microchips production for a sustainable future
Partner News
■ Silvaco Names Chris Zegarelli as Chief Financial Officer
Business News
■ Flanders Welcomes Europe’s First Photonic Chip Factory
■ TSMC raises prices. Tech giants and consumers will pay for geopolitics
■ CG Power to MosChip Technologies: Five semiconductor stocks to watch out for in 2025






ASIL-B Compliant 1G-25G MACsec Security Module (select configurations)
• Supports Media Access Control Security (MACsec) IEEE 802.1AE standard
• Full-duplex inline MACsec Security Modules work seamlessly with Synopsys Ethernet IP

What they said at
IP SoC Silicon Valley 25

USB4 - Advanced USB Interface for broad market
Hiral Patadiya, Sr. Tech Manager, System Level Solutions, Inc.

Power Management Sensors and LDO for Datacenter, AI and Chiplets
Rolly Baradiya, Circuit Design Engineer, Analog Bits Inc.

Architectures and IP for SoC Clocking
Jeff Galloway, Principal/ Co-Founder, Silicon Creations

Efficient by Design: Revolutionizing Power Management in SoCs
Floriberto Lima, CEO, SiliconGate

Cost-effective AI MCU featuring a standard logic compatible embedded flash memory
Peter Song, CEO and Co-Founder, ANAFLASH Inc.

How do you select the right memory architecture and choose between LPDDR, GDDR, and HBM?
Dirk Seidel, Marketing Director, Innosilicon

Building Tomorrow Today: Innovating with IP
Ook Kim, CEO, 4lynx, Inc.

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