D&R News Alert
September 11th, 2025


Welcome to the issue of September 11th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Do not miss D&R IP Soc China 2025
Now Open!

Foundry and Foundry Ecosystem
■ Intel 14A node confirmed more expensive than 18A due to High-NA EUV
Analog IP
■ Perceptia Begins Port of pPLL03 to Samsung 8nm Process Technology
Mixel MIPI C-PHY/D-PHY Combo IP in TSMC N5, N6, and N7 
  • Silicon Proven in TSMC N5 and N6
  • MIPI C-PHY v2.0/MIPI D-PHY v2.5 compliant
  • Up to 41.04Gbps aggregate data rate
Join Mixel at the TSMC North America OIP Ecosystem Forum 2025 (Booth #715) – September 24

Memory IP
■ Deca and Silicon Storage Technology Announce Strategic Collaboration to Enable NVM Chiplet Solutions
Interconnect
■ Network on Chip (NOC) IP Core Now Offered Under Whitebox License: Full Source Code, Unlimited Usage, Complete Modification Rights
Securing the Software-Defined Era with PUF-based HSM Edge Server
Ememory • Unique PUF fingerprints secure identity and keys.
• FIDO integration ensures full control of key access.
• Beyond automotive OTA, securing diverse smart devices.
Explore PUF Technology >>

Interface IP
■ Valens Semiconductor and Samsung partner to enhance the MIPI A-PHY standard
Design platform
■ Perforce's Delphix AI used in software development to boost speed and security
Xiphera
Xiphera's TRNG IP Core
• High-entropy randomness for secure keys
• NIST compliant
• Pure RTL with no hidden CPU/software
• FPGA & ASIC ready
 Learn more >>
Meet us at FPGA Horizon in London, Oct 7!

RISC-V
■ SiFive details second generation RISC-V cores for AI accelerators
Artificial Intelligence
■ Cadence Expands Digital Twin Platform Library with NVIDIA DGX SuperPOD Model to Accelerate AI Data Center Deployment and Operations
■ ASML partners with Mistral AI on lithography innovation
■ Smarter, Faster, More Personal AI Delivered on Consumer Devices with Arm’s New Lumex CSS Platform, Driving Double-Digit Performance Gains
■ Nvidia Specializes GPU for First Stage of Transformer Inference
■ China's AI Chip Ambitions Limited by HBM Memory Supply, Notes Report
■ New light-based chip boosts power efficiency of AI tasks 100 fold
Rambus
Rambus Design Summit: Memory Solutions for Next-Generation Intelligent Systems

• Join us virtually on October 8th for a morning of sessions exploring AI
• Explore the impact of memory and interconnect technologies on AI performance, scalability, and efficiency across data centers and edge devices
• Dive into the latest memory IP standards like HBM4, LPDDR5, GDDR7, PCIe 7, and CXL 3 that drive next-gen AI
• Hear expert talks on AI’s impact on memory design, demand, and innovation.
 Save Your Seat >>

Security
■ Agile Analog announces deal with tier 1 US customer for agileSecureanti-tamper IP on TSMC N4P
■ Jmem Tek has achieved NIST CAVP certification, with ASCON algorithm implementation, and will be showcased at SEMICON Taiwan.
Multimedia
■ Auracast broadcast audio solution powers assistive listening in public spaces with Nordic Semiconductor wireless connectivity
■ IntoPIX JPEG XS Powers Barnfind BarnPalette Flow-XS For Next-Generation Broadcast Workflows
Partner News
■ BrainChip Appoints James Shields as Vice President of Sales and Business Development
Business News
■ Opticore up to $14M in Funding as Company Seeks to Advance Photonic Computing Chips
■ Quantinuum Raises $600 Million to Drive Scalable Quantum Computing
■ TSMC Releases August 2025 Revenue Report
■ Arm Goes for Rebrand for Mobile CSS, Drops Cortex, Immortalis





New IP
• NavIC LDPC/ BCH Decoder FEC by Global IP Core Sales
• 56G Ethernet PHY by Qualitas Semiconductor
• Embedded flash IP, 1.5V/5V SMIC 90nmBCD by Floadia Corporation
• OmniGate by Comcores
• 2.5G BaseT Ethernet PHY IP in TSMC 22ULL by T2M GmbH
• 24-bit PDM to PCM 115 dB SNR PLL-less 4 channels by Dolphin Semiconductor

What they said at
IP SoC Silicon Valley 25

makeChip: an accessible, cost-effective, and cloud-based Chip Design Platform
Florian Bilstein, Director Design Service, Racyics GmbH

Challenges of Porting ASIC IP Cores to FPGA: Tricky but Worthwhile!
Ettore Giliberti, Senior Staff Application Engineer, SmartDV Technologies

DFT Ready in RTL Level with SOC Canvas
Ahchan Kim, CTO, ITDA Semiconductor Co., Ltd.

PVT Monitors fulfilling the desire for increasing levels of control in Advanced nodes for complete Silicon Lifecycle management in SoCs
Rohan Bhatnagar, Product Manager, Synopsys, Inc.

Securing Devices/embedded Systems Lifecycle management
Karthik Raj Shekar, Field Application Engineer presales & Junior Project Manager, Secure-IC

Interview with Justin Endo - Director, Marketing & Sales - Mixel, Inc.

Interview with Nidish Kamath - Director of Product Management for Memory Interface IP - Rambus, Inc.

Interview with Steven Brightfield - Chief Marketing Officer - BrainChip Inc.

REGISTER:
If this newsletter was forwarded to you by a colleague, you can have it sent directly to you at no cost. To register for D&R SoC News Alert, go to:

UPDATE YOUR PROFILE / UNSUBSCRIBE :
You are subscribed as and you receive this Alert in html format.

* If you wish to unsubscribe, you can do it there: