D&R News Alert
December 4th, 2025


Welcome to the issue of December 4th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

IP-SoC EU 2025 Open! Watch now >>

Design Platform
■ NVIDIA and Synopsys Announce Strategic Partnership to Revolutionize Engineering and Design
Chiplets
■ Open Chiplet Design Moves Forward with Tenstorrent’s OCA Plan
The Rambus LPDDR5T/5X/5 Controller
Rambus • Boosts performance to 9.6 Gbps
• Supports device densities up to 32Gb
• For mobile, automotive, IoT, PC laptops, and edge devices
• Available standalone or integrated with your choice of PHY
• Add-on cores available
 Learn More >>

Embedded Memory
■ Attopsemi I-fuse® OTP was successfully adopted by Wiliot for IoT Pixels
Security
■ DCD-SEMI Unveils Ultra-Fast DAES IP Core for AES Encryption
■ Idaho Scientific Selects QuickLogic eFPGA Hard IP to Enable Crypto Agility
■ From Launch to Leadership: The Microservice Store Nominated for TechWorks Cybersecurity Award
Artificial Intelligence
■ Certus Semiconductor adopts AI-powered Solido to accelerate IO library, analog IP and ESD development
■ The AI Future is Now All About the Edge
Automotive
■ Arteris Selected by Black Sesame Technologies for Next Generation of Intelligent Driving Silicon
■ VeriSilicon’s NPU IP VIP9000NanoOi-FS has achieved ISO 26262 ASIL B certification
New Technology
■ imec to open new R&D hub in Qatar, boosting silicon photonics and chip design
■ Fraunhofer HHI advances indium phosphide photonics for high-speed data communication
■ Not a hallucination: AI will be running on Silicon Photonics
Partner News
■ Semidynamics Welcomes Iakovos Stamoulis as Chief Technology Officer
■ BOS Semiconductors at 2025 Korea Tech Festival
Business News
■ Could an EU Chips Act 2.0 Bridge the Lab-to-Fab Gap?
■ Germany Redirects Intel Funds Into New Wave of Semiconductor Projects





New IP
• The FortifyIQ Compact AES-SX AES Encryption Core with Robust SCA/FI Protection for Constrained Devices by FortifyIQ, Inc.
• WIFI6/BLE 5.2/BT 5.0 Dual Band RF IP (RFIP) in TSMC22 by Jiujiu Intelligent Technology
• UALink TL by Chip Interfaces ApS
• Ultra Accelerator Link（UALink) Controller by CoMira Solutions Inc.

What they said at
IP-SoC EU 25

Unlocking Generative AI at the Edge: How LPDDR enables Scalable & Efficient Intelligence
Sebastien Person, SPE Field Applications Engineering, Rambus, Inc.

The Compiler-Free Revolution: Model-Specific ASICs as the Definitive Architecture for Sub-1W Edge AI Accelerators
Richard Wu, General Manager, DeepMentor USA

From Firmware to Cloud: Building PQC-Consistent Security Architectures
Léo BELLALI, Junior Field Application Engineer, Secure-IC

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