D&R News Alert
February 9th, 2026


Welcome to the issue of February 9th, 2026 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Rambus
Secure by Design:
A Rambus Webinar Series
• Weekly webinar series focused on cutting-edge hardware security
• Get practical guidance for building resilient products against evolving threat vectors
• Topics include: Tamper-resistant devices, Root of Trust, MACsec, IME, Quantum Safe Cryptography, and Certified Silicon IP
 Register Today >>

Foundry News
■ TSMC to make advanced 3nm chips in Japan
■ GF partners with Telsys to expand Israel presence
Packaging Solutions
■ Chiplets Get Physical: The Days of Mix-and-Match Silicon Draw Nigh
■ Synopsys Lightmatter Alliance Highlights Bet On AI Chip Connectivity IP
Design Platform
■ Transforming Chaos Into Clarity: Keysight Data Management for the AI Era – by Keysight
■ FAMES pilot line inaugurated after delivering first validated semiconductor results
Analog IP
■ Creating a Frequency Plan for a System using a PLL – by Perceptia
Dreamchip Specialized FEC and Connectivity Cores
• Advanced Features Wireless Modems
• High Performance Forward Error Correction
• FPGA or ASIC
 Learn More >>

RISC-V
■ Phison Selects Andes RISC-V Cores for its First aiDAPTIV+ AI Solution, Marking a Major Milestone in AI Architecture
■ Fabless Startup Aheesa Tapes Out First Indian RISC-V Network SoC
Automotive
■ VeriSilicon Enhanced ISP8200-FS Series IP Achieves ASIL B Functional Safety Certification
■ Arasan's ultra low power MIPI D-PHY IP achieves ISO26262 Certification
Internet of Things
■ Exclusive Interview: Mika Jäsberg Discusses CoreHW’s RTLS Offering
Artificial Intelligence
■ Omni Design Technologies Advances 200G-Class Co-Packaged Optics IP Portfolio for Next-Generation AI Infrastructure
Security
■ EnSilica joins CHERI Alliance to boost chip security
■ Siemens unveils virtualised substation protection platform
Photonics
■ Tower Semiconductor & Nvidia team up on 1.6T silicon photonics for AI data centers
Green Electronics
■ Biodegradable PCB targets short-lifetime electronics
Business News
■ Dnotitia Readies IPO After Turning AI Memory Bottlenecks into a New Semiconductor Category
■ 2026 Outlook with Coby Hanoch of Weebit Nano
■ Inside FAMES: How Europe Depends on RTO Collaboration
■ STMicroelectronics expands strategic engagement with Amazon Web Services to enable new high performance compute infrastructure for cloud and AI data centers
■ European firms eye investments in finance, semiconductors, AI in Vietnam
■ Record quarter for Arm






Synopsys eUSB2V2 Device Controller IP
• Converts between eUSB2 and USB 2.0 signaling levels, enabling an SoC with eUSB2 PHY to...
• Designed for mature process nodes

What they said at
IP-SoC EU 25

European policies on Semiconductors : from Chips Act1 to Chips Act 2.0
Dominique THOMAS, STMicroelectronics

Meet IC-DASH, The French Design Enablement Team of the European Chip Design Platform
Alexandre Valentian, CEA

A software and hardware AI platform for efficient deployment at the edge
Alexandre Valentian, CEA

SLM IP and Analytics
Graham Woods, Synopsys, Inc.

AI-assisted IP & SoC Verification: Making It Right
Francois Cerisier, CEO, AEDVICES

Liberating Functional Verification from Boolean Shackles
Vikas Sachdeva, Senior Director of Product Strategy and Business Development, Real Intent Inc.

REGISTER:
If this newsletter was forwarded to you by a colleague, you can have it sent directly to you at no cost. To register for D&R SoC News Alert, go to:

UPDATE YOUR PROFILE / UNSUBSCRIBE :
You are subscribed as and you receive this Alert in html format.

* If you wish to unsubscribe, you can do it there: