D&R News Alert
April 23rd, 2026


Welcome to the issue of April 23rd, 2026 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Do not miss IP-SoC
Silicon Valley 2026 		Now Open! >>

Foundry Ecosystem News
■ TSMC Debuts A13 Technology at 2026 North America Technology Symposium
■ Synopsys Partners with TSMC to Power Next-Generation AI Systems with Silicon Proven IP and Certified EDA Flows
■ Siemens collaborates with TSMC to advance AI for semiconductor design
■ Cadence Collaborates with TSMC to Accelerate Design of Next-Generation AI Silicon
■ Silicon Creations Celebrates 20 Years of Global Growth and Leadership in 2nm IP Solutions
Silicon Library SD4.0 UHS-II complete one-stop solution
• Industry standard solution for both Host and Device
• SD4.0 UHS-II PHY in various processes, technologies
• SD4.0 UHS-I, -II controller logic
 Learn more >>

Design and Monitoring Platform
■ Detect diagnose & debug using sensors & functional monitors – By Movellus & Siemens EDA
Memory Interface Standard
■ JEDEC® Previews LPDDR6 Roadmap Expanding LPDDR into Data Centers and Processing-in-Memory
Ensuring device identity,
security, & lifecycle resilience 		Ememory
PUF-based product portfolio
• PUFrt : Unique ID & key generation, storage, management
• PUFcc : Authentication & Attestation
• PUF-PQC : PQC-ready for future-proof security
• PUFhsm : Hardware-isolated trusted execution
Visit Us at
D&R IP-SoC,
IEEE HOST,
and CYBERSEC >>

RISC-V
■ Wind River Joins the CHERI Alliance and Collaborates with Innovate UK to Accelerate Cybersecurity Innovation
Security
■ DCD-SEMI expands its cryptographic CryptOne system with EdDSA Curve25519 IP core for secure embedded systems
■ Menta’s eFPGA Technology Adopted by AIST for Cryptography and Hardware Security Programs
■ Crypto Quantique and Attopsemi Unite PUF and I-fuse® OTP technology to Deliver Zero-Overhead Device Enrollment on FinFET Technology
■ AI has compressed the attack timeline
UDP & RTP Controller SystemVerilog IP
Digital Block • UDP/IP Offload with Optional RTP Support
• AXI4 Memory-Mapped & AXI4-Stream Interfaces
• High Throughput, Low-Latency Operation
• Configurable Multi-Channel / Multi-Session Design
Learn more...

Artificial Intelligence
■ Arteris and MIPS Partner to Accelerate Development for Physical AI Platforms
■ LLMs in Transition: What Research, Real World Practice, and Europe Are Driving Forward Today
Automotive
■ Arasan achieves the Industry’s First ASIL-D Certification for its CAN XL IP Core
■ MIPI A-PHY Tx and Rx IP Cores: Production-Proven, 6.4 Gbps Automotive Connectivity in 12FFC
Application-Specific Processors (ASIPs) for Physical AI
Synopsys When: Apr 29, 2026 | 7:00 AM PST
Speaker: Dr. Falco Munsche
Technical Product Marketing, Synopsys
 Register Now >>

Networking
■ Credo to Highlight Next-Generation Connectivity Solutions for AI Infrastructure at TSMC 2026 Technology Symposium
Green Electronics
■ Earth Week 2026: Advancing sustainable manufacturing for the essential technologies the world relies on
SCHAEFFLER Power Electronic Inverter, On-Board Charger and DCDC converters designed
for reduced e-waste

Interview with Olivia Belorgeot - Schaeffler

Photonics News
■ Europe’s best-performing stock of 2026 rides AI photonics wave
Partner News
■ Dnotitia Closes KRW 90 Billion Series A to Accelerate AI Storage Expansion
Business News
■ European Consortium Launches €50 Million SPINS Pilot Line to Industrialize Semiconductor Quantum Chips
■ TSMC Q1 revenue tops $35.9bn on strong 3nm demand
■ EU unlocks €63M to accelerate AI in health and safety






1600G MACsec HPC Security Module
• With the Synopsys MACsec Security Modules, SoC designers can take advantage of the following:
• Supports Media Access Control Security (MACsec) IEEE 802.1AE standard

What they said at
IP-SoC EU 25

European policies on Semiconductors : from Chips Act1 to Chips Act 2.0
Dominique THOMAS, STMicroelectronics

Meet IC-DASH, The French Design Enablement Team of the European Chip Design Platform
Alexandre Valentian, CEA

SLM IP and Analytics
Graham Woods, Synopsys, Inc.

AI-assisted IP & SoC Verification: Making It Right
Francois Cerisier, CEO, AEDVICES

Liberating Functional Verification from Boolean Shackles
Vikas Sachdeva, Senior Director of Product Strategy and Business Development, Real Intent Inc.

A software and hardware AI platform for efficient deployment at the edge
Alexandre Valentian, CEA

Standardizing CDC and RDC abstract models
Jean-Christophe Brignone, SMTS, STMicroelectronics
Agile Analog microphone

Why anti-tamper sensors matter
Chris Morrison, Agile Analog

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