D&R News Alert
Innovation in the Semiconductor World
May 14th, 2026

Welcome to the issue of May 14th, 2026 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Foundry News
■ Apple-Intel Foundry Deal Could Reshape U.S. Chip Manufacturing
Design Platform
■ LTSCT Expands Advanced Power Design Capabilities with Synopsys
■ Siemens unveils AI-powered library characterization to accelerate semiconductor design
■ Siemens democratizes EDA software access for European electronics industry through the Chips JU European Chips Design Platform (EuroCDP) project
■ CEA-Leti Platform Offers Chipmakers Nanometre- Scale Strain Mapping
Hardware Root of Trust for Agentic AI Ememory
• Anchor AI agent trust in silicon, not software
• PUFrt + PUFcc: silicon Root of Trust IP block
• Deployed: SecuX dongles built on PUFcc + PUFrt
• SecuAI 360: PUF + FIDO + DID + HSM + blockchain
Explore our PUF-based security IPs
& SecuX products >>

Chiplets
■ EXTOLL announces Availability of Industry´s first 16G UCIe PHY IP in GlobalFoundries 22FDX/22FDX+ Ready for Customer Integration
Analog IP
■ TES Electronic Solutions GmbH is extending its on-chip sensor IP portfolio for X-FAB’s XT018 - 0.18µm BCD-on-SOI technology
IP Cores from CAST give you a Better IP Experience:
CAST • Royalty-Free RISC-V Processors: Low-Power & FuSa
• Security engines: PQC, AES, MACsec, Secure Boot
• Advanced connectivity: TCP/UDP/IP, TSN, CAN XL
Proven & Reliable Products • Industry-Leading Support
 Learn more >>

RISC-V
■ OSYX Technologies and Andes Technology Announce Strategic Collaboration on RISC-V Virtualization
■ SiFive Sets New Bar for High-Performance RISC-V with Third-Generation Performance P550 and P570 IP
■ HighTec EDV-Systeme and SiFive: Together strengthening the RISC-V Ecosystem for Safe and Secure Automotive and Industrial Applications
Honchen New: Edge AI NPU IP - CNN & Generative AI Editions
• CNN Edition: ~0.5 TOPS, low-power, DDR-less
• Generative AI Edition: ~1 TOPS, Whisper/LLM/TTS
• Process-flexible RTL Protected Code, FPGA-verified
• Licensed by a listed semiconductor company
 Explore Both Editions >>

Audio/Video
■ Chips&Media Completes Development of Next-Gen 'AV2' HW Decoder IP
Automotive
■ Aeva Adopts Cadence Tensilica Vision DSP to Advance Lidar Performance and Efficiency
Wireless
■ Ceva Advances Full-Stack Wireless Vision with Next Generation Bluetooth High Data Throughput and Integrated RF Design Win
Green Electronics

Synano New Materials for Green Electronics

Interview with Fateh Sana & Srikanth Birudula - Synano

Partner News
■ QuickLogic Announces New Seven-Figure FPGA Hard IP Contract
■ eMemory Technology Inc Q1 2026 Earnings Call Highlights: Record Revenue Growth and Strategic Expansion
Business News
■ Europe’s Photonics Push Runs Through Spain
■ TSMC Board of Directors Meeting Resolutions
■ Korean economy projected to expand 2.5% in 2026 on chips: KDI





16G UCIe-SP PHY - GlobalFoundries 22FDX/22FDX+
• Line rates up to 16Gbps, also supporting UCIe defined speeds of 4, 8, and 12Gbps.
• 16 bi-directional lanes

What they said at
IP SoC Silicon Valley 26
Correva microphone

Interview with Ali Khan - co-CEO - Correva, Inc.

Bringing Tenstorrent's Ascalon RISC-V CPU IP to life via playable Doom
Rae Parnmukh, Director, IP Product Operations, Tenstorrent

The New RISC-V Spectrum of AI Compute
Oliver Jones, CEO, Aion Silicon

Multimedia AI application in edge device – evolution and how to prepare
Andy Lee, Vice president, US marketing, Chips&Media, Inc.

Architecting a Flexible Root of Trust Across SoC Security Frameworks with PUFrt
Matthew Yu, Marketing Manager, eMemory Technology Inc.

Building Trust in the Age of AI and Quantum Threats
Sara Tehranipoor, Lead Application Engineer, Secure-IC A Cadence Company

Securing Physical AI Systems: From Device Identity to Distributed Trust
Ranga Desikachari, Director of Engineering, Crypto Quantique

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