D&R News Alert
Innovation in the Semiconductor World
June 18th, 2026

Welcome to the issue of June 18th, 2026 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Foundry and Technology News
ASML, TSMC and imec bring industry-ready 2D-material transistors closer with breakthrough 300mm integration
Intel Foundry Details Process Milestones and Future Innovation at VLSI Symposium
UK Semiconductor Centre and Rapidus partner to expand access to advanced chip technologies
CEA-Leti Scales Ferroelectric RAM to 22nm Node, Unlocking Denser, More Efficient Memory for Edge AI
Chiplets
UCIe Full Signal Integrity Analysis Flow
Analog Bits to Present at EE Times Virtual Event, "The Road To Chiplet Scalability" on June 24th, 2026
Design and Monitoring Platforms
Synopsys Announces Availability of the First Wave of Multiphysics Fusion Solutions
Keysight Expands Photonic Design Automation Portfolio with System-Level Simulation
Introducing Tessent UltraSight - a complete functional monitoring & debug solution for SoCs
Interface IP
MIPI Alliance Welcomes Sony Semiconductor Solutions as a Promoter Member
Allegro DVT
Allegro DVT's Pulsar Decoder IP now supports AV2 video codec
Pulsar™ D440: Real-Time Multi-Standard Decoder IP with AV2 support
Sirius™ AV2: Compliance Test Suites for encoder and decoder validation
Astralis™ AV2: Bitstream Analyzer for advanced AV2 stream analysis
Learn more about our latest developments by reading our
Pulsar D440 AV2 Decoder IP press release.

Multimedia IP
Allegro DVT’s Pulsar Decoder IP adds support for AV2 video codec
Chips&Media Signs Next-Gen 'AV2' Video IP Licensing Deal with North American Big Tech, Strengthening Global Standards Leadership
RISC-V
Baya Systems partners with Openchip for RISC-V systems
PCIe Gen6/5 Controller & PHY IP for AI/HPC SoCs
• Gen6 (PAM4) / Gen5 backward compatible
• Low power, low latency architecture
• Advanced node ready (≤7nm)
• Controller + PHY integrated solution
• Hot IPs: MIPI A-PHY, DDR5/LPDDR5

Artificial Intelligence
Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE
Gov’t joins hands with Samsung to support AI chip development
Security Solutions
Agile Analog collaborates with Xiphera for Post-Quantum Cryptography challenge
Xiphera contributes to SecureSoC, strengthening Finland’s cybersecurity, security of supply, and semiconductor expertise
Fraunhofer IPMS unveils Q‑Dice: Quantum Random Number Generator delivering multi‑Gbps true randomness for secure applications
Floadia eFlash qualified by AG1 on TSMC 180BCD
Rambus • Automotive eFlash IP on TSMC 180BCD Gen3
• AEC-Q100 Grade 1 with fast erase <20ms
• No PDK change, built-in charge pump & ECC
Learn More >>

Automotive
Quintauris and Nuclei Cooperate to Ensure Automotive Real-Time RISCV Readiness with RT-Europa
Imagination Technologies Brings GPU Expertise to CHASSIS’ New Chiplet Project
Internet of Things
Europe’s first sovereign chip manufacturing flow could reshape the IoT supply chain
Webinar: A Digital Product Passport (DPP) for the electronics industry : Status, use cases and outlook
When: July 6th, 2026 | 3:00pm - 4:30pm (Paris Time)
Click here to register! >>

Business News
Fraunhofer calls for faster technology transfer to strengthen Germany
Qualcomm Shares Rise on Tenstorrent Deal Talks and AI Push





What they said at
IP SoC Silicon Valley 26


High performance, Low Power IP calibration
Esko Mikkola, Alphacore, Inc.


Managing Power and Performance in the Age of AI
Pranshu Kalra, Analog Bits Inc.


SLM PVT IP Tutorial in N2P GAA tech node using DAA architecture
Rohan Bhatnagar, Product Management, Synopsys, Inc.

Innosilicon microphone

Interview with Farzad Zarrinfar - Senior Vice President of Sales & Marketing - Innosilicon


New SRAM IP to break AI SoC Memory Wall
Dr. KyungRok Kim, CEO, Ternell


The Widespread Use of LPDDR Memory Subsystems
Byul Choi, Head of Sales & Marketing, OPENEDGES Technology, Inc.


Memory controller solutions for Edge AI Applications
Ravi Thummarukudy, CEO, Mobiveil Inc.


AI Inference needs a mix-and-match memory strategy
Nidish Kamath, Director of Product Management, Silicon IP, Rambus, Inc.


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