Panelists at DesignCon Feb. 3 agreed that just shipping RTL code for silicon IP is far from sufficient. But what comprises a “total” IP solution for SoC integration? That’s a little more complicated, and it fueled a good discussion with panelists from Arasan Chip Systems, Atrenta, Virage Logic, and Cadence.
I found this discussion particularly interesting because not enough attention has been paid to the challenges of integrating IP onto an SoC. The EDA industry has primarily focused on the creation of IP. When you start to think about what it takes to provide IP that is ready for integration, the list can get pretty long.
“In order to provide a smooth IP integration flow,” said panel chair Ram Gopalan, senior director of corporate marketing at Arasan, “IP providers need to go beyond just providing the RTL IP.” A “total” IP requirement starts with architectural modeling and includes verification IP (VIP), software drivers and stacks, and hardware platforms for development and validation, he said.
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