There's a lot of excitement about 3D ICs with through-silicon vias (TSVs), and one reason is that stacked die can provide very fast memory access. That's why wide I/O is emerging as a significant new direction for 3D ICs - and why the March 28 Cadence announcement of the first wide I/O memory controller IP may help spur the coming era of 3D integration.
Wide I/O memory is a new DRAM technology and an emerging JEDEC standard that calls for a 512-bit wide interface and 12.8GB/second bandwidth. In addition to high bandwidth, it promises low power consumption. It will initially target the mobile consumer marketplace, where space is at a premium, performance and power demands are stringent, and there is already a movement toward 3D ICs.
While wide I/O does not technically require 3D ICs with TSVs, that's what it is really aimed at, said Marc Greenberg, product marketing director at Cadence. "Wide I/O is really a TSV technology," he said. "There is really no other practical way you could achieve a 512-bit interface to DRAM in a mobile device." Indeed, you would not want to route 512 signal lines on a printed circuit board, and trying to implement wide I/O with wire bonding would require a lot of extra wiring. However, in addition to stacked die configurations, wide I/O memory could be used in silicon interposer implementations with side-by-side die.
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