Think RTL synthesis is a solved problem that needs no further discussion? Think again. In a keynote speech at the recent International Symposium on the Quality of Electronic Design (ISQED 2013) Sanjiv Taneja, vice president of product engineering at the Cadence Front-End Design group, showed how advanced node IC design is raising new requirements for "physical aware" logic synthesis.
The keynote was titled "Physical Aware, High Capacity RTL Synthesis for Advanced Nanometer Designs." Taneja discussed the physical effects of interconnect and congestion, and showed how these effects place new demands on RTL synthesis starting with logic structuring, global mapping, and incremental optimization. He illustrated the capabilities that are needed in order to model physical effects in synthesis.
Why is a new RTL synthesis approach needed? The mobile revolution is driving a new generation of devices, Taneja said. 20nm ICs are often in the "multi GHz" range with interconnect delay and routing congestion limiting the performance, and they may have 100M+ placeable instances. Add to that complex clocking schemes, power management techniques, and lithography and design for manufacturability (DFM) concerns, and massive complexity is the outcome.
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