Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow CEI (10)
arrow Cell / Packet (6)
arrow Error Correction/Detection (152)
arrow Ethernet (177)
arrow Fibre Channel (1)
arrow HDLC (6)
arrow Interleaver/Deinterleaver (1)
arrow Modulation/Demodulation (22)
arrow Optical/Telecom (35)
arrow Other (15)
425 IP
51
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
52
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
53
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
54
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
55
10.0
10G / 25G UDP/IP Hardware Protocol Stack UDP UDPIP
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...
56
10.0
40G / 50G UDP/IP Hardware Protocol Stack UDP UDPIP
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...
57
10.0
EA/MZ Modulator Driver 1.25Gb/s to 11.3Gb/s
The PMCC_EAMD12G is designed to directly drive the inputs of EA or MZ Modulators or EML devices at data-rates up-to 11.3Gbps. The driver features prog...
58
10.0
UALink PCS
The Chip Interfaces UA Link PCS IP Core is a high-performance, silicon-agnostic and fully compliant Physical Coding Sublayer (PCS) implementation of U...
59
10.0
UDP/IP Hardware Protocol Stack UDP UDPIP
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...
60
10.0
Reed Solomon Forward Error Correction Encoder Decoder
The Reed Solomon Forward Error Correction (RS FEC) IP is a highly optimized and silicon agnostic implementation of the RS FEC encoder and decoder algo...
61
10.0
IEEE1588 & IEEE802.1AS PTP Hybrid Clock (HC) core
The PTP Hybrid Clock (HC) from NetTimeLogic is a combination of NetTimeLogic's PTP Transparent Clock (TC) and PTP Ordinary Clock (OC). It adds the Syn...
62
10.0
IEEE1588 & IEEE802.1AS PTP Timestamp Unit (TSU) core
NetTimeLogic’s PTP Timestamp Unit is an implementation of a single port Frame Timestamp Unit (TSU) according to IEEE1588-2008 (PTP). It detects PTP fr...
63
10.0
Serdes 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10GbE, XFI, Back Plain
PMCC_SERDES12G is a macro-block consisting of a 32:1 serializer and 1:32 deserializer with supporting functions such as CDR, CMU, loop-backs, LOL, LOS...
64
10.0
oFEC Encoder and Decoder
OpenROADM oFEC (Open Forward Error Correction) is a core element of the OpenROADM initiative, providing a standardized, open-source FEC solution for h...
65
10.0
1G IP/UDP full HW Stack Transmitter / Receiver
To efficient transfer large amount of data and off-load the system processor, BitSim has launched its IP, Bit-UDP Ethernet. This core is a real-tim...
66
10.0
5G-NR LDPC Decoder
5G NR is the mobile broadband standard of the 5th generation. A new rate compatible structure for LDPC codes are employed for channel coding to fulfil...
67
10.0
Wideband DDC
The Creonic Wideband Digital Down Converter (DDC) digitally converts the input signal at IF frequency down to baseband by multiplying input samples wi...
68
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
69
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY (in production)...
70
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
71
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
72
10.0
Gigabit Ethernet PHY (Modification Right)
Gigabit Ethernet PHY Modification Right (in production)...
73
10.0
UltraFast BCH Decoder
BCH codes are widely used where bit errors are scattered randomly within the codeword. The Creonic Ultra-fast BCH Decoder is capable of processing an ...
74
10.0
NR-5G Polar Decoder and Encoder IP Core
The Forward Error Correction (FEC) sub-system is one of the essential basing blocks in any communication systems so a powerful FEC code is needed. The...
75
10.0
Ethernet IPSec/MACSec Switch/Router IP Core - Efficient and Massively Customizable
Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide...
76
10.0
Ethernet Switch / Router IP Core - Efficient and Massively Customizable
Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide...
77
10.0
Ethernet TSN Switch IP Core - Efficient and Massively Customizable
Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide...
78
10.0
NTP Server core
NetTimeLogic’s NTP Server is a full hardware (FPGA) only implementation of a SNTPv4 Server according to RFC 4330/5905. It supports hardware timestampi...
79
10.0
Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
"The CetraC EndSystem IP coreis the ideal solution to link your Avionic Computer System to a safe & secure embedded network as ARINC664p7, TSN or Safe...
80
10.0
DVB-S2 Modulator IP Core
DVBS2_TX.vhd is the transmitter top level component. Inputs consist of one or several streams (transport, generic). The output is a DDR complex baseba...
81
10.0
DVB-S2X Demodulator
The Creonic DVB-S2X demodulator is a low-complexity high-performance solution that allows for symbol rates of up to 100 MSymb/s on state-of-the-art FP...
82
10.0
DVB-S2X Demodulator ASIC silicon proven IP Core
...
83
10.0
DVB-S2X Modulator
The Creonic DVB-S2X high performance modulator performs all tasks of an inner transmitter. The modulator expects BBFrames after mode adaptati...
84
10.0
DVB-S2X Wideband LDPC/ BCH Decoder
The Creonic DVB-S2X wideband decoder is a scalable solution that allows for symbol rates of up to 500 MSymb/s on state-of-the-art FPGAs...
85
8.5077
56G Ethernet PHY (8nm)
The Ethernet PHY IP consists of hardmacro PMA, PMD and softmacro PCS compliant to IEEE 802.3 Ethernet specification. This IP offers a cost-effective a...
86
8.0
10/100 Base-TX Fast Ethernet PHY; SMIC 40nm LL
SP-10_100_Ethernet-S40LL is a single-port DSP-based Fast Ethernet Transceiver. It contains all the active circuitry required to convert data stream to...
87
8.0
10/100 Ethernet PHY for TSMC 22nm ULP
10 100ETHERNET-T22ULP18 is a single-port DSP-based Fast Ethernet Transceiver. It contains all the ac?tive circuitry required to convert data stream to...
88
8.0
10/100 Ethernet PHY, TSMC 28nm HPC+
-10 100ETHERNET-T28HPCP18 is a single-port DSP-based Fast Ethernet Transceiver. It contains all the ac?tive circuitry required to convert data stream ...
89
8.0
CCSDS LDPC Encoder and Decoder
The CCSDS LDPC codec supports code rate 223/255 with coded block size of 8160 bits, which allows for a simple replacement of legacy Reed-Solomon decod...
90
8.0
SDA OCT V3.0 Encoder and Decoder
The Optical Communications Terminal (OCT) Standard was developed by the Space Development Agency (SDA) with the purpose of bringing interoperability a...
91
8.0
LDPC Decoder for 802.11
This is an LDPC decoder compliant with the IEEE 802.11 n/ac/ax standards. It supports high throughput,...
92
8.0
Reed Solomon Decoder
CYB-RS-de core implements the Reed Solomon decoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum nu...
93
8.0
Reed Solomon Encoder
CYB-RS-en core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum nu...
94
8.0
1Gbit/s LDPC Decoder and Encoder (WiMedia UWB)
The solution from Creonic for data rates of up to 1 Gbit/s offers outstanding efficiency in terms of implementation complexity. John Porter, CTO of Ca...
95
8.0
Single port 10/100 Fast Ethernet Transceiver - TSMC12nm FFC
SP-10 100ETHERNET-T12FFC is a single-port DSP-based Fast Ethernet Transceiver. It contains all the active circuitry required to convert data stream t...
96
8.0
DVB-GSE Encapsulator and Decapsulator
The DVB-GSE encapsulator and decapsulator IP cores close the gap between network protocols like Ethernet and the physical layer of the DVB family of s...
97
8.0
DVB-RCS2 Modulator
The Creonic DVB-RCS2 modulator is a low-complexity high-performance solution that allows for symbol rates of up to 160 MSymb/s on state-of-the-art FPG...
98
8.0
DVB-RCS2 Multi-Carrier Receiver
DVB-RCS2 (Digital Video Broadcast – Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digit...
99
7.0
CCSDS 131.2 Wideband Modulator
The Creonic CCSDS high performance modulator performs all tasks of an inner transmitter. The modulator expects SCCC (Serial Concatenated Convolutional...
100
7.0
Doppler Channel IP Core
The Creonic Doppler Channel IP is a Doppler shift frequency (DSF) generator capable of introduce a shift frequency to samples as a phase offset. The I...