Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow CEI (10)
arrow Cell / Packet (6)
arrow Error Correction/Detection (152)
arrow Ethernet (177)
arrow Fibre Channel (1)
arrow HDLC (6)
arrow Interleaver/Deinterleaver (1)
arrow Modulation/Demodulation (22)
arrow Optical/Telecom (35)
arrow Other (15)
425 IP
151
5.0
Time Sensitive Networking (TSN) IIC(R) Plugfest Application core
The TSN Industrial Internet Consortium(R) (IIC) Plugfest Application is a companion core for the TSN IP cores from NetTimeLogic. The IIC(R) Plugfest A...
152
5.0
DMESCC - Enhanced Multiprotocol Serial Communication Controller
The DEMSCC – Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit microprocessors. The DMESCC...
153
5.0
OPEN Alliance TC6 10BASE-T1S MACPHY Interface
The CT25209 Digital IP core implements the MACPHY SPI protocol defined by the “OPEN Alliance TC6 Serial 10BASE-T1x MACPHY Interface specifications”. ...
154
5.0
SPI Serial Peripheral Interface Master/Slave
The CC-SPI-AXI is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller. The SPI core can be efficiently implemen...
155
5.0
Ethernet MAC & PCS 10G/25G
Comcores Ethernet MAC and PCS 10G/25G is a silicon agnostic implementation of the IEEE 802.3 standard. The Ethernet MAC IP includes the Reconsiliation...
156
5.0
Ethernet MAC 10G SFP
The ETH_MAC_10G_SFP IP incorporates one Ethernet MAC at 10Gbits on a FPGA and is compliant with IEEE802.3ae specification. It is designed to be con...
157
5.0
Ethernet MAC 10G/25G
Comcores Ethernet MAC 10G/25G IP solution enables the host to communicate data using the IEEE 802.3 standard for the respective speeds and is suited f...
158
5.0
Ethernet MAC 10M/100M/1G/2.5G
Comcores Ethernet MAC 10M/100M/1G/2.5G IP solution enables the host to communicate data using the IEEE 802.3 standard for the respective speeds and is...
159
5.0
Ethernet MAC 40G/100G
Comcores Ethernet MAC 40G/100G IP solution enables the host to communicate data using the IEEE 802.3 standard for the respective speeds and is suited ...
160
5.0
Ethernet Switch 10G
Comcores Ethernet Switch 10G IP core is a highly configurable and size optimized implementation of a non-blocking switch that allows continuous transm...
161
5.0
Ethernet Switch 1G/10G
Comcores Ethernet Switch 1G/10G IP core is a highly configurable and size optimized implementation of a non-blocking crossbar switch that allows conti...
162
5.0
Ethernet TSN Advanced Switch 10M/100M/1G/10G/25G for 5G/ORAN and other applications
Comcores Manticore 10M/100M/1G/10G/25G IP is an advanced Ethernet Switch with an extensive set of QoS features and statistics. The switch supports up ...
163
5.0
Ethernet TSN Advanced Switch 10M/100M/1G/10G/25G for Aerospace
Comcores Manticore 10M/100M/1G/10G/25G IP is an advanced Ethernet Switch with an extensive set of QoS features and statistics. The switch supports up ...
164
5.0
Ethernet TSN MAC 10G/25G
Comcores TSN MAC 10G/25G provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Preemption and ...
165
5.0
Ethernet TSN MAC 10M/100M/1G/2.5G
Comcores TSN MAC 10M/100M/1G/2.5G provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Preemp...
166
5.0
NTP Client core
NetTimeLogic’s NTP Clientis a full hardware (FPGA) only implementation of a SNTPv4 Client according to RFC 4330/5905. It supports hardware timestampin...
167
5.0
DVB-RCS2 Turbo Decoder
DVB-RCS2 (Digital Video Broadcast - Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digit...
168
5.0
DVB-S2X Wideband LDPC BCH Decoder IP Core
The DVB-S2X Wideband LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 ...
169
5.0
DVB-T2 Demodulator and LDPC/ BCH Decoder IP Core
The demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system has an internal state machine to cont...
170
5.0
Synchronous Ethernet (SyncE) ESMC and Enhanced ESMC core
NetTimeLogic’s Synchronous Ethernet (SyncE) Node is a full hardware (FPGA) only implementation of an ESMC frame Handler and State selector. The whole ...
171
4.0
LDPC Decoder for DVB-T2/T2-Lite
In Digital video broadcasting for terrestrial broadcasting systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Chec...
172
4.0
LDPC Decoder for IS-GPS-800D Applications
The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parity Check (LDPC) Forwar...
173
4.0
Reed Solomon Decoder IP Core
A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error c...
174
4.0
Reed Solomon Encoder IP Core
A high performance, fully configurable Reed Solomon Encoder IP Core that is intended for use in a wide range of applications requiring forward error c...
175
4.0
Highly Integrated Reed Solomon Codec
ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several ...
176
4.0
Single Channel HDLC Controller
Noesis Technologies ntHDLC single channel High-Level Data Link Controller (HDLC) is a full-duplex transceiver with independent transmit and receive un...
177
4.0
Smart Grid PLC Baseband Processor
The ntG3_BBP is a fully compliant ITU-T G.9903 baseband modem that can be used in a wide range of smart grid applications over power lines, including ...
178
4.0
Interleaver / De-interleaver
Configurable interleaving/deinterleaving function that can be used in a wide range of applications that employ channel coding....
179
4.0
Home Plug Green PHY MAC Layer TX/RX
ntHPGP_MAC IP core implements “Connectionless CSMA-Only Level-0 CCo“ MAC Layer functionality with Passive Coordination, as detailed in Chapter 5 of “H...
180
4.0
Non-binary LDPC Decoder
A powerful Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems. Low-Density Parity-Check (LDPC) codes are ...
181
4.0
Configurable Reed Solomon Decoder
Highly configurable Reed Solomon Decoder compliant with the requirements of nearly all modern standards using Reed-Solomon error correction....
182
4.0
Configurable Reed Solomon Encoder
A fully configurable Reed Solomon Encoder compliant with the requirements of nearly all modern standards that use Reed-Solomon error correction....
183
4.0
Configurable Soft Output Demapper
Noesis Technologies Soft Output Demapper is a structural element of any modern telecom system. The receiver extracts the phase and magnitude of the ca...
184
4.0
Configurable Turbo Product Codec
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the...
185
4.0
Configurable Viterbi Decoder
Highly configurable Viterbi Decoder compliant with the requirements of nearly all modern standards using Viterbi error correction....
186
4.0
Programmable OFDM Channel Estimator
The wideband OFDM signal suffers from frequency selective fading. Therefore it is necessary to identify and invert the discrete transfer function of t...
187
4.0
ITU G.704 E1 Framer/Deframer
Noesis Technologies ntE1_G704 Framer/Deframer is designed for E1 networks and is compliant with ITU recommendations G.704, G.706, G.732, G.775 and O.1...
188
4.0
ITU G.704 T1 Framer/Deframer
Noesis Technologies ntT1_G704 Framer/Deframer is designed for T1 networks and is compliant with ITU recommendations G.704, G.706, G.732, G.775 and O.1...
189
4.0
Fully Configurable LDPC Encoder
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the...
190
3.0
100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj)
The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 802.3bj (100G Backplane...
191
3.0
66/2112 Codec for Cyclic Code (2112,2080)
The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3ap (10G Backplane Ethe...
192
3.0
19 GHz to 20.25 GHz FMCW Modulator for RADAR
The WEA20SFMCWI22G is an ultra-linear FMCW modulator consisting of 3 integrated PLLs. One PLL provides a high frequency Reference signal and the other...
193
3.0
MAC - DMAC-RMII - 10/100 Mb Media Access Controller with RMII
Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. The DMAC-RMII in cooperation with ...
194
3.0
BCH Encoder/Decoder
The binary BCH decoder has four main functional blocks along with memory blocks: 1. Syndrome calculation block: identifies the presence of errors in ...
195
3.0
NCR Processor
NCR (Network Clock Reference) is a procedure to provide the master clock (i.e. time information) of the satellite to all its user terminals. Typically...
196
3.0
High-Performance Lossless Compression Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...
197
3.0
Open Source Viterbi Decoder (AXI4-Stream compliant)
Convolutional codes are widely adopted in wireless communication systems for forward error correction. Creonic offers you an open source Viterbi decod...
198
3.0
DVB-S2 BCH and LDPC Encoder and Decoder
DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites....
199
2.0
2.3 Gbit/s DOCSIS 3.1 Downstream LDPC Decoder (PLC, NCP, Data)
Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications standard that permits the addition of high-bandwidth d...
200
2.0
MAC Privacy Protection IP
The MAC Privacy Protection IP is a fully compliant solution that provides Ethernet Layer 2 Security for port and data privacy as standardized in IEEE ...