Design & Reuse
54 IP
51
0.0
DVinsight - Correct by construction SV UVM code with a smart editor
DVinsight™ is a smart editor for creation of Universal Verification Methodology (UVM) based System Verilog (SV) Design Verification (DV) code.DV...
52
0.0
NVMe-Xactor VIP Solution
NVMe-Xactor is a comprehensive VIP solution portfolio for NVMe 1.2 used by SoC and IP designers to ensure comprehensive verification and protocol and ...
53
0.0
Hybrid Emulation
Hybrid emulation is performed where some parts of the system run in the emulator and other parts run in a virtual prototyping. As a byword for early a...
54
0.0
Symphony Mixed-Signal Platform
The industry s fastest and most configurable mixed-signal solution to accurately verify design functionality, connectivity, and performance across A/D...