Design & Reuse
3915 IP
1
70.0
Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
Ceva-Waves Links is a versatile family of multi-protocol wireless platform IPs, encompassing the latest consumer wireless standards. It leverages the ...
2
50.0
Multi-protocol wireless plaform integrating 802.11ax (Wi-Fi 6), Bluetooth 5.4 Dual Mode, 802.15.4 (for Thread, Zigbee and Matter)
Ceva-Waves Links is a versatile family of multi-protocol wireless platform IPs, encompassing the latest consumer wireless standards. It leverages the ...
3
40.0
LDPC Decoder for 5G NR and Wireless
Mobiveil's 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance. It...
4
0.0
LTE UE PHY layer
The PHY baseband covers all Synchronization Signals, downlink and uplink Physical Channels, libraries, algorithms integrated with cross-functional log...
5
0.0
LTE UE Protocol Stack HW (Arm, Cortex A8)
Mymo offers 3GPP LTE Release-9 UE FDD and TDD UE Protocol Stack on Arm hardware . The Integrated solution of MAC-RLC-PDCP-RRC-NAS-TCP-IP with several ...
6
0.0
LTE UE Protocol Stack Software
Mymo offers 3GPP LTE Release-9 UE FDD and TDD UE Protocol Stack software. The software is in ANSI C ported at RT-Linux kernel level ideally suited for...
7
0.0
mioty - The Wireless IoT Technology
Wireless data transmission systems are being increasingly deployed in industrial and home automation applications. These robust systems are used to tr...
8
3.0
10GHz to 15GHz broadband wireless microwave receiver front-end
The WEA1015R130G is a complete broadband wireless microwave receiver front-end operating in the frequency band spanning from 10 GHz to 15 GHz. Impleme...
9
3.0
10GHz to 15GHz broadband wireless microwave transceiver front-end
The WEA1015T130G is a complete broadband wireless microwave transceiver front-end operating in the frequency band spanning from 10 GHz to 15 GHz. Impl...
10
1.0
NFC wireless interface supports ISO14443 A and B
The IP block provides the physical layer implementation of ISO 14443 interface. In particular, it includes the necessary functional devices for receiv...
11
1.0
NFC wireless interface supports ISO14443 A and B
The IP block provides the physical layer implementation of ISO 14443 interface. In particular, it includes the necessary functional devices for receiv...
12
0.0
EFR32 Mighty Gecko Mesh Networking Wireless SoCs for zigbee and Thread
The Mighty Gecko family of SoCs is ideal for designing energy-friendly wireless connected IoT devices. Part of the Wireless Gecko portfolio, the Might...
13
0.0
Wireless USB Device Controller
HCL has developed the Device controller for wireless USB which converts the wired USB2.0 device packets to wireless packets based on WUSB specificatio...
14
0.0
Wireless USB Host Controller
HCL has developed the Device controller for wireless USB which converts the wired USB2.0 device packets to wireless packets based on WUSB specificatio...
15
0.0
Complete FEC Encoder Solution compliant to LTE/ LTE A Specification
The Lekha IP – 3GPP LTE FEC Encoder IP Core V1.0 addresses the implementation of the FEC building blocks compliant to 3GPP TS 36.212 V 10.5.0. S...
16
0.0
eSi-MediSense - Wireless Medical Sensor - Customisable ASIC Platform
The eSi-MediSense is a customizable ASIC platform for ultra-low-power wireless vital signs and medical monitoring products. This versatile platform al...
17
0.0
STM32L4 Discovery kit IoT node, low-power wireless, BLE, NFC, SubGHz, Wi-Fi
The B-L475E-IOT01A Discovery kit for IoT node allows users to develop applications with direct connection to cloud servers. The Discovery kit enables ...
18
200.0
Post-Quantum Cryptography - xQlave® PQC ML-KEM (Kyber)
In a world where advances in quantum computing threaten traditional cryptographic systems, Xiphera’s xQlave® ML-KEM (Kyber) Key Encapsulation Mechanis...
19
104.0
LPDDR5X, LPDDR5, LPDDR4X, LPDDR4 Combo PHY & Controller
The INNOSILICON™ LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller. It is fully compliant with the JEDEC standard. Optimized for low-power a...
20
100.0
PCIe 5.0 PHY & Controller
The Innosilicon Gen1/2/3/4/5 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, h...
21
105.0
CME IoT platform
Sensor-Mate (sensing node)Long distance wireless communication (920MHz)Sensor-Gateway (Aggregator)920MHz wireless module (CM Engineering proprietary)G...
22
100.0
MACsec - Extreme-speed - Security Protocol
MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera's comprehensive MACsec solution portfolio safeguards th...
23
100.0
Post-Quantum Cryptography - nQrux® Secure Boot - Quantum-Secure Authenticated Boot (PQC)
nQrux® Secure Boot enhances system security by enabling quantum-secure authenticated boot, crucial for verifying the authenticity and integrity of bin...
24
100.0
Post-Quantum Cryptography - xQlave® PQC ML-DSA (Dilithium)
The xQlave® ML-DSA (Dilithium) Digital Signature Algorithm IP core secures critical infrastructures and operations against the threat of quantum compu...
25
60.0
UCIe Chiplet PHY & Controller
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
26
51.0
TLS 1.3 - Security Protocol
Transport Layer Security (TLS) is a cryptographic protocol used for building a secure connection between a client and a server over the Internet. A ha...
27
51.0
True Random Number Generator (TRNG)
The TRNG IP core establishes a benchmark for hardware-based security in cryptographic systems, by generating high-entropy, true random numbers essenti...
28
50.0
MAXVY Technologies
MAXVY is a fast growing fabless semiconductor company which is currently engaged in the fields of RTL design and Verification IP Solutions. We offe...
29
50.0
AES - GCM - Extreme-speed variant
Xiphera's AES symmetric encryption IP cores ensure robust encryption and decryption, providing data confidentiality and integrity with the Advanced En...
30
50.0
IPsec - Security Protocol
IPsec (Internet Protocol Security) is a widely implemented protocol to secure communications across the Internet. Xiphera’s IPsec core enhances secure...
31
30.0
GDDR7 PHY & Controller
The INNOSILICON™ GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode. In PAM3 mode, each b...
32
48.0
nQrux® Crypto Module
Xiphera’s nQrux® Crypto Module IP core provides a comprehensive security platform that allows for customisation of top-notch cryptographic services, s...
33
25.0
HBM4, HBM3E PHY & Controller
INNOSILICON™ HBM4/3E IP is fully compliant with the JEDEC standard for HBM3E and the preliminary specification for HBM4. The IP includes a customizabl...
34
25.0
DDR5, DDR4 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR5/4 Combo PHY s provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDR...
35
43.0
Elliptic Curve Cryptography (ECC) Accelerator
The high-speed ECC Accelerator reaches to more than a thousand operations per second in a modern FPGA or ASIC. Furthermore, it covers all NIST P curve...
36
15.0
GDDR6X, GDDR6 Combo PHY & Controller
The INNOSILICON™ GDDR6X/6 PHY is fully compliant with the JEDEC GDDR6X/6 standard, supporting data rates of up to 20 Gbps per pin for PAM2 GDDR6 mode ...
37
25.0
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver
The SVRPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture ...
38
2.0
HBM3, HBM3E PHY & Controller
This document describes a general layout scheme and Innosilicon HBM3/3E PHY connecting to the controller using a DFI digital interface. All interface ...
39
2.0
Innosilicon - High-Quality ASIC Customization Services
With a team of first-class experts, highly-reliable chip customization ability, and rich experience in mass production on processes from 55nm to 5nm, ...
40
1.0
10G Multi-SerDes PHY
The Innosilicon 10G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 10Gbps within a single lane. The PHY can be configured ...
41
1.0
12.5G Multi-SerDes PHY
The Innosilicon 12.5G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 12.5Gbps within a single lane. For this particular da...
42
1.0
32G Multi-SerDes For PCIe5.0/USB3.x PHY
The Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this datasheet, the PH...
43
1.0
32G Multi-SerDes PHY + Controller
The INNOSILICON™ 32G Multi-SerDes PHY is a highly configurable IP solution capable of supporting data rates of up to 32 Gbps per lane. It is designed ...
44
1.0
64G/56G SerDes
The Innosilicon 64G/56G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 56Gbps within a single lane. For this datasheet, th...
45
1.0
25G Multi-SerDes PHY
The Innosilicon 25G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datash...
46
1.0
HBM2E PHY&Controller
Innosilicon HBM2E PHY IP is a silicon proven product with max speed up to 3600Mbps per DQ data, HBM2E memory has 1024bit DQ, total bandwidth can be 3....
47
1.0
HBM2E/2 Combo PHY&Controller
Innosilicon HBM2E/2 Combo PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible HBM devices. It is optimized ...
48
1.0
HBM3/2E Combo PHY&Controller
The third-generation HBM (HBM3/2E) technology, outlined by the JESD235C standard, inherits physical 128-bit DDR interface with 2n/4n prefetch architec...
49
1.0
PCIe 4.0 Controller
The Innosilicon Gen1/2/3/4 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, hig...
50
1.0
PCIe 4.0 PHY
The Innosilicon PCIe4.0 PHY is a highly configurable PHY capable of supporting speeds up to 16Gbps within a single lane. For this particular datasheet...