Design & Reuse
5809 IP
3651
0.0
PCIe 7.0 PHY in TSMC (N7A, N5A, N3A) for Automotive
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...
3652
0.0
UCIe Controller for Streaming Protocols
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
3653
0.0
PCIe Controller Testbench
PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design. This includes the following features: • R...
3654
0.0
UCIe PHY IP on TSMC N3P
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
3655
0.0
UCIe PHY on Samsung SF5A
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...
3656
0.0
UCIe PHY on TSMC N3E
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...
3657
0.0
PCIe Switch for USB4 Hubs, Hosts and Devices
Rambus PCIe Multi-port Switch for USB4 is a customizable, embedded Switch for PCI Express (PCIe) designed for implementations in USB4 devices. A fully...
3658
0.0
UCIe-A PHY for Advanced Package (x64) in Samsung (SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
3659
0.0
UCIe-A PHY for Advanced Package (x64) in Samsung (SF4X)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
3660
0.0
UCIe-A PHY for Advanced Package (x64) in TSMC (N5)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
3661
0.0
UCIE-A PHY, 5nm/4nm
The InPsytech (IPT) UCIe-A PHY is a mass-production proven, state-of-the-art physical layer interface designed to provide exceptional performance and ...
3662
0.0
UCIE-A PHY, ADVANCED PACKAGE
The InPsytech (IPT) UCIe-A PHY is a state-of-the-art physical layer interface, offering industry-leading power efficiency and proven in mass productio...
3663
0.0
UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
3664
0.0
UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
3665
0.0
UCIe-S PHY for Standard Package (x32) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
3666
0.0
CCIR 656 Decoder
The Digital Blocks DB1840 CCIR 656 Decoder IP Core decodes an ITU-R BT.656 digital video uncompressed NTSC 720x486 (525/60 Video System) and PAL 720x5...
3667
0.0
CCIR 656 Encoder
The Digital Blocks DB1830 CCIR 656 Encoder IP Core encodes 4:2:2 Y’CbCr component digital video with synchronization signals to conform to NTSC & PAL ...
3668
0.0
PCM to Class D Amplifier
The AR35S13B is a high-performance digital Class D Amplifier IP for mono speaker playback application. The amplifier converts 16-24 bits digital PCM (...
3669
0.0
ACS-AIP-DPHY-40GF-Auto - MIPI D-PHY in GlobalFoundries 40nm Automotive Process
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
3670
0.0
ACS-AIP-DPHY-40LP-RA - MIPI D-PHY TSMC 40LP Renesas- Automotive Grade
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
3671
0.0
Active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency
RFDBL03C is an active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency within the IC to feed in and drive th...
3672
0.0
Active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency
RFDBL04C is an active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency within the IC to feed in and drive th...
3673
0.0
3D GPU compatible with OpenGL ES (3D Graphics API) and OpenCL (Computing API)
DMP M3000 3D GPU IP Core adopts 3rd generation 3D graphics architecture Musashi and make remarkable progress in PPA (Power, Performance, Area) perform...
3674
0.0
3D GPU supporting OpenGL ES2.0 capability
The DMP ant300 is the world’s smallest class 3D graphics IP core supporting OpenGL ES2.0 capability. It is the premiere solution for popular ASIC/ASSP...
3675
0.0
2D Graphics IP Core
DMP K3000 2D GPU IP Core offers the most powerful rendering performance in the industry, with a minimum area solution. You will witness blazing font a...
3676
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2D Graphics Rendering Engine
Digital Blocks 2D Graphics Hardware Accelerator Verilog IP Cores consists of the DB9200AXI4, DB9200AXI, DB9200AHB, and DB9200AVLN. The DB9200 2D Graph...
3677
0.0
MD5 Hashing Core
The es1005 hash fully implements the MD5 (Message Digest Algorithm RFC 1321). The core can be used for data authentication in digital broadband, wire...
3678
0.0
VDC-M (VESA Display Compression-M) Decoder
The Rambus VESA VDC-M 1.2 Decoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliv...
3679
0.0
VDC-M (VESA Display Compression-M) Encoder
The Rambus VESA VDC-M 1.2 Encoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 encoder to deliv...
3680
0.0
HDCP 2.0 Encryption Suite
HDCP Suite consists of hardware and software components implementing the HDCP 2.0 protocol. The hardware components are fully synchronous and availabl...
3681
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HDCP Encryption-Decryption Engine
The Trilinear Technologies High-bandwidth Digital Content Protection (HDCP) Encryption-Decryption Engine IP core allows system designers to accelerate...
3682
0.0
HDCP Engine
The EIP-116 High-bandwidth Digital Content Protection Control Path module provides the required technology for implementing all the secure access, cry...
3683
0.0
SDIO HOST VMM based Verification IP
The Secure Digital Input Output (SDIO) interface is a card interface defined to connect a SD Host Controller with four different types of cards, namel...
3684
0.0
3DIO PHY IP for TSMC N5
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
3685
0.0
HDMI 2.1 Forward Error Correction (FEC) Receiver
The HDMI Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol de-interleaving/de-mapping as specified by the HDMI 2....
3686
0.0
HDMI 2.1 Forward Error Correction (FEC) Transmitter
The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specified by the HDMI 2.1 ...
3687
0.0
HDMI 2.1/DisplayPort 2.1 TX PHY in Samsung (SF4A) for Automotive
The Synopsys HDMI 2.1 TX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide th...
3688
0.0
HDMI 2.1/DisplayPort 2.1 TX PHY in Samsung (SF5A)
The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...
3689
0.0
HDMI 2.1/DisplayPort eDP 1.4 TX PHY in TSMC (N6C, N4C)
The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...
3690
0.0
UDP/IP Hardware Protocol Stack - 100G
The Digital Blocks DB-UDP-IP-100GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 100 GbE n...
3691
0.0
UDP/IP Hardware Protocol Stack - 10G
The Digital Blocks DB-UDP-IP-10GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 10 GbE net...
3692
0.0
UDP/IP Hardware Protocol Stack - 1G
The Digital Blocks DB-UDP-IP-1GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 10 GbE netw...
3693
0.0
UDP/IP Hardware Protocol Stack - 25G
The Digital Blocks DB-UDP-IP-25GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 25 GbE net...
3694
0.0
UDP/IP Hardware Protocol Stack - 40G
The Digital Blocks DB-UDP-IP-40GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 50 GbE net...
3695
0.0
UDP/IP Hardware Protocol Stack - 50G
The Digital Blocks DB-UDP-IP-50GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 50 GbE net...
3696
0.0
LDPC for 5G DVBS2 802.11
Encoder: - Every H-matrix (out of 102, 51 for BG1, and 51 for BG2 in 5G) has its encoder, which is just a bunch of XOR gates and co...
3697
0.0
DDR2 SDRAM VIP
Double-Data-Rate-Two Synchronous Dynamic Random Access Memory (DDR2 SDRAM) is the memory technology used for high speed data transfer. This class of m...
3698
0.0
DDR3 Memory Controller
Rambus’s DDR3 Controller Core offered by Rambus is designed for use in applications requiring high memory throughput, high clock rates and full progra...
3699
0.0
DDR3/3L/DDR4/LPDDR4 PHY
The DDR3, DDR3L, DDR4, and LPDDR4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected to a third-...
3700
0.0
DDR4 Memory Controller
Rambus DDR4 Controller Core from Rambus is designed for use in applications requiring high memory throughput, high clock rates and full programmabilit...