Design & Reuse
5161 IP
151
2.5
SATA HOST Controller on Cyclone IV GX
The LDS SATA HOST C4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Cyclone IV GX FPGA. The ...
152
2.5
SATA Host Controller on Spartan 6 LXT FPGA
The LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA. The LDS SATA HOST SP6 IP is co...
153
2.5
SATA Host controller on Virtex 5 FXT
The LDS SATA HOST XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...
154
2.5
SATA Host Controller on Virtex 6 LXT
The LDS SATA HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA HOST XV6 IP is com...
155
2.5
SATA Host on Altera Arria II GX
The LDS SATA HOST AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The L...
156
2.5
SATA Host on Xilinx Zynq Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS SATA 3 H...
157
2.5
SATA HOST Synchronous IP
The LDS SATA HOST XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...
158
2.5
SATA III HOST Controller on Virtex 6
The LDS SATA 3 HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 FPGA. The LDS SATA 3 ...
159
2.5
SATA RECORDER ON VIRTEX 6
The LDS SATA RECORDER XV6 IP is a complete recorder system IP. It can be configured according the recording performance required and the quantity of ...
160
2.5
SATA RECORDER ON VIRTEX 7 GTX
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161
2.5
LDS SATA RECORDER IP ON ARTIX 7
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162
2.5
LDS SATA RECORDER ON KINTEX 7
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163
2.5
LDS SATA RECORDER ON ZYNQ
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164
2.5
Serial ATA Dual Host Controller
The LDS_SATA HOST DUAL XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XV5...
165
2.5
Serial protocol Interface Slave
The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master. The MSPIS IP can be ...
166
2.5
Xilinx Kintex 7 NVME HOST IP
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....
167
2.5
Xilinx Ultra Scale NVME Host IP
The LDS NVME HOST K7U IP is one of the most flexible NVME HOST IP in the market. It has been done for beginners and expert in NVMe to drive NVMe PC...
168
2.5
Xilinx Ultra Scale Plus SATA HOST IP
The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4 FPGA. The LDS_SATA3_...
169
2.5
Xilinx UltraScale Plus NVME Hhost IP
The LDS NVME HOST ZUP IP is one of the most flexible NVME HOST IP in the market. It has been done for beginners and expert in NVMe to drive NVMe PC...
170
2.5
Xilinx ZYNQ NVME HOST IP
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....
171
2.5
Kintex Ultra Scale Plus NVMe Host IP
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. The LDS NVME HOST IP provides two interfaces : * On...
172
2.5
Virtex 7 GTX SATA 3 Host Controller
The LDS SATA 3 HOST XV7X IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 7 GTX speed grade 2 FPGA. The LDS SA...
173
2.5
Universal Asynchronous Receiver / Transmitter
The macro M16550, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a microprocessor and a ser...
174
2.5
Universal Asynchronous Receiver Transmitter
The macro M16450, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a microprocessor and a ser...
175
2.5
Logic Design Solutions - Design Services
Logic Design Solutions has a deep knowledge of FPGA & IP design. We have an expertise in fast designs and for over 20 years? experience in FPGA/PLD De...
176
2.5
Polarfire NVMe Host Recorder
The LDS NVME HOST RECORDER IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. The register file interface simplify the manag...
177
2.5
Polarfire SoC NVMe Host
The LDS NVME HOST RECORDER IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. The register file interface simplify the manag...
178
2.5
SPI Master - EEPROM Controller
The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI slave. The MSPIM IP can...
179
2.5
ARINC 429 IP
The M429GEN IP implements a synchronous single-chip ARINC 429 Transmit and Receive Controller capable of linking one CPU to one or several ARINC 429 ...
180
2.5
ARINC 429 Synchronous Transmitter Receiver
The M429T1R1 macro implements a synchronous single-chip ARINC 429 Transmit and Receive Controller Macro capable of linking one CPU to one ARINC 429 bu...
181
2.5
Artix Ultra Scale Plus NVMe Host IP Gen4
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. - The LDS NVME HOST IP provides two interfaces : o One C...
182
2.5
Ethernet MAC 10G SFP
The ETH_MAC_10G_SFP IP incorporates one Ethernet MAC at 10Gbits on a FPGA and is compliant with IEEE802.3ae specification. It is designed to be con...
183
2.5
Dual SATA Host controller on Virtex 5 FXT FPGA
The LDS SATA HOST DUAL XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XF5...
184
2.5
NVME Host IP
The new NVME-HOST-IP of Logic Design Solutions enables now random access in addition to the existing sequential access and multi-user access. FAT32 fi...
185
2.5
NVMe Host Recorder on Mini-ITX Zynq 7
The LDS NVME HOST RECORDER IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. The register file interface simplify the manag...
186
2.5
NVME-HOST-IP VIRTEX 7
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....
187
2.5
EXFAT IP Soft Core for NVMe
The EXFAT IP Soft Core for NVMe supports any disk size and enables to reach the same speed as in raw format. One directory is created for each recordi...
188
2.5
Synchronous Universal Asynchronous Receiver/Transmitter
The macro MUART, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a microprocessor and a seri...
189
2.5
ZYNQ SATA 3 AHCI Host Controller with Linux Driver
The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed gr...
190
2.0
7 way DDR combo
The LPDDR2/3_DDR3/4 libraries contain the 7-way combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and the ...
191
2.0
7 way DDR combo
The LPDDR2/3_DDR3/4 libraries contain the 7-way combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and the ...
192
2.0
1.2V GPIO
The 1.2V GPIO library provides a bidirectional I/O driver for Parallel Trace Interface applications. This cell is compliant with version 2.0 of the th...
193
2.0
1.2V GPIO library designed for the SVID three-line interface.
The 1.2V GPIO library provides an open-drain bi-directional I/O driver designed for the SVID three-line interface. It is compliant with the Intel SVID...
194
2.0
3.3V Fault Tolerant General Purpose I/O Inline Pad Set
The 3.3V GPIO FT library provides general purpose bidirectional I/O cells that are fault tolerant. These programmable, multi-voltage I/O’s give the sy...
195
2.0
3.3V Fault Tolerant General Purpose I/O Staggered Pad Set
The 3.3V GPIO FT library provides general purpose bidirectional I/O cells that are fault tolerant. These programmable, multi-voltage I/O’s give the sy...
196
2.0
3.3V General Purpose I/O Inline Pad Set
The 3.3V GPIO library provides general purpose bidirectional I/O cells. These programmable, multi-voltage I/O’s give the system designer the flexibili...
197
2.0
3.3V General Purpose I/O Staggered Pad Set
The 3.3V GPIO library provides general purpose bidirectional I/O cells. These programmable, multi-voltage I/O’s give the system designer the flexibili...
198
2.0
3.3V 100 MHz Oscillator I/O Pad Set
The 1.8V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spa...
199
2.0
3.3V 100MHz Oscillator I/O Pad Set
The 3.3V 100MHz Oscillators library includes a programmable oscillator macro I/O cell. ▪ 100 MHz programmable oscillator These libraries are off...
200
2.0
3.3V 100MHz Oscillator IO Inline Pad Set
The 3.3V 100MHz Oscillators library provides a 100 MHz crystal oscillator macro I/O cell. An adapter cell is included to utilize this oscillator with ...