Design & Reuse
244 IP
1
35.0
Radiation-Hardened eFPGA
QuickLogic’s radiation-hardened eFPGA IP uses the company’s proven Australis eFPGA IP generation flow to provide customizable eFPGA IP optimized for s...
2
0.0
eFPGA IP and FPGA Software for any foundry/process
QuickLogic Corporation (NASDAQ: QUIK), a leading developer of embedded FPGA (eFPGA) Hard IP and User Tools, and ruggedized FPGAs, QuickLogic has over...
3
0.0
eFPGA IP and FPGA Software for any TSMC 12nm
QuickLogic Corporation (NASDAQ: QUIK), a leading developer of embedded FPGA (eFPGA) Hard IP and User Tools, and ruggedized FPGAs, QuickLogic has over...
4
0.0
eFPGA IP and FPGA Software for GF22FDX
QuickLogic Corporation (NASDAQ: QUIK), a leading developer of embedded FPGA (eFPGA) Hard IP and User Tools, and ruggedized FPGAs, QuickLogic has over...
5
0.0
eFPGA IP and FPGA Software for Intel 18A
QuickLogic Corporation (NASDAQ: QUIK), a leading developer of embedded FPGA (eFPGA) Hard IP and User Tools, and ruggedized FPGAs, QuickLogic has over...
6
0.0
eFPGA IP and FPGA Software for UMC 22nm
QuickLogic Corporation (NASDAQ: QUIK), a leading developer of embedded FPGA (eFPGA) Hard IP and User Tools, and ruggedized FPGAs, QuickLogic has over...
7
60.0
IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology
IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology...
8
60.0
TSMC CLN16FFGL+ HBM PHY IP
This datasheet describes GUC’s HBM (High Bandwidth Memory) PHY IP, which can be integrated with HBM memory controller to provide HBM functionality. Th...
9
60.0
TSMC CLN5FF HBM PHY IP
This datasheet describes GUC HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. Th...
10
60.0
TSMC CLN6FF/7FF Die-to-Die Interface PHY
IGAD2DX01A is a high speed die-to-die interface PHY which transmits data through INFO RDL channels. IGAD2DX01A contains 32 Tx lanes and 32 Rx lanes pe...
11
60.0
Multi-Die interLink (GLink 2.3) IP
GUC multi-die interLink (GLink) IP provides world’s best class solution for high-bandwidth, low-power, low-latency multi-channel interconnection in a ...
12
40.0
Camera SLVS-EC 3.0 Receiver 10.0Gbps 8-Lane
* The CL12812M8RIP10000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL12812M...
13
30.0
Camera SLVS-EC/MIPI D-PHY/sub-LVDS/CMOS1.8 combo Receiver 5.0G/2.5G/1Gbps/166MHz 8-Lane
* The CL12842M8RM3AM5AIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL1284...
14
30.0
UFS Host Controller 4.1 IP
The UFS Host Controller Interface (UFSHCI) is a high-performance interface that connects to UniPro and M-PHY IP in mobile platforms. It provides comma...
15
30.0
Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
* The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams. A phase-locked clock is t...
16
30.0
Low jitter 4.96GHz to 5.6GHz PLL in TSMC N40
PMCC_PLL5GN40 is a PLL IP block which synthesizes low-jitter (<0.3ps RMS) 4.96GHz to 5.6GHz (5.28GHz typical) clock signals from the 620-700MHz refere...
17
30.0
PVT Sensor TSMC 40G
The PVT Sensor is an IP block which monitors chip Process, Voltage, and Temperature (PVT) providing a high accuracy measurement result. The sensor con...
18
25.0
Superscalar Out-of-Order Execution Multicore Cluster
AndesCore™ AX65 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on AndeStar™ V5 architectu...
19
20.0
Camera SLVS-EC 2.0 Receiver 5.0Gbps 8-Lane
* The CL12812M8RIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL12812M8RI...
20
20.0
PCIe 4.0 PHY in TSMC(6nm,7nm,12nm,16nm)
M31 PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 4.0 IP suppo...
21
20.0
PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
M31 PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 5.0 IP suppo...
22
20.0
MIPI C-PHY/D-PHY Combo(5nm, 7nm, 12/16nm, 28nm, 40nm, 55nm)
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...
23
20.0
MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)
MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pi...
24
20.0
USB4 Gen3X2 and DP1.4 X4 PHY IP with Type-C connector support
M31 USB4 Gen3x2 transceiver IP provides a complete range of USB4 Gen3x2 host and peripheral applications up to 40Gbps. It is compliant with the PIPE5....
25
16.0
USB2.0 Host Transceiver PHY
USB 2.0 HOST Transceiver is a fully integrated PHY Core which is a super-set of HOST PHY with High Speed (HS), Full-Speed (FS) and Low-Speed Transceiv...
26
15.0
Camera SLVS-EC 3.0 Transmitter 10.0Gbps 8-Lane
* The CL12811M8TIP10000 TXPHY supports 8 TX DATA lanes for up to 10Gbps application. A wide range phase-locked clock is embedded in the IP to suppor...
27
12.0
PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
SMS5000 is a fully integrated CMOS transceiver that handles the full Physical Layer PCI Express protocol and signaling. It contains all necessary AFE ...
28
12.0
Serial ATA (SATA) I/II PHY IP CORE
SMS6000 is a Serial ATA gen I and gen II compliant PHY IP which supports SAPIS and Serial Attached SCCI (SAS) specifications both at 1.5 Gbp/s and 3.0...
29
12.0
Fibre-Channel Transceiver
SMS3000 is a fully integrated CMOS transceiver compliant with ANSI X3T11 Fiber Channel standards. It contains all necessary Clock synthesis, Clock Rec...
30
12.0
Gigabit Ethernet For Fiber & STP/COAX Transceiver PHY
Gigabit Ethernet Transceiver for Fiber, Short Length Copper, STP and COAX....
31
12.0
SONET/SDH OC-3 / OC-12 Transceiver/CDR PHY
Innovative architecture to meet the SDH/ Sonet Jitter Spec utilizing deep sub-micron single poly CMOS process Fully in compliance with ANSI, Bellcore...
32
12.0
USB 2.0 Device Transceiver PHY
...
33
12.0
USB 2.0 OTG On-The-Go Transceiver PHY
SMS USB 2.0 OTG Transceiver is LS/FS/HS compliant with USB 2.0 specification and includes VBUS comparators, Switched Pullup & Pulldown resistors, data...
34
10.0
EA/MZ Modulator Driver 1.25Gb/s to 11.3Gb/s
The PMCC_EAMD12G is designed to directly drive the inputs of EA or MZ Modulators or EML devices at data-rates up-to 11.3Gbps. The driver features prog...
35
10.0
Rad-hard 17-bit 3-channel sigma-delta ADC at 3.2kS/s
Pacific Microchip Corp. is offering a radiation hardened 3-channel sigma-delta ADC. The ADC achieves 16.5-bit ENOB at 3.2kS/s rate. The ADC can operat...
36
10.0
Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
The CL12822M4R2JM2LIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP. The CL12822M4...
37
10.0
Serdes 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10GbE, XFI, Back Plain
PMCC_SERDES12G is a macro-block consisting of a 32:1 serializer and 1:32 deserializer with supporting functions such as CDR, CMU, loop-backs, LOL, LOS...
38
10.0
MIPI D-PHY/sub-LVDS/CMOS1.8 combo Transmitter 2.5G/800Mbps 8-Lane
The CL12661M8T1KM2JIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System. The CL12661M8T1KM2JIP is designed to support...
39
10.0
SLVS-MI/MIPI-DPHY Transmitter 4-Lane 2500Mbps
The CL12821I4T2JM2NIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System. The CL12821I4T2JM2NIP2500 converts the...
40
10.0
UniPro 1.6 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
41
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
42
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
43
10.0
UniPro Controller 2.0 IP (host / device)
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
44
10.0
Up to 60GHz Divide By 2 Prescaler with I and Q outputs in GiGe
The PMCC_DIV60G is a high speed (up to 60GHz) fully differential static frequency divider by 2, designed using Jazz SiGe120 (SBC18HX) technology. Diff...
45
10.0
USB 3.2 Gen2/Gen1 PHY IP in TSMC(3nm, 5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps. It is compl...
46
10.0
Automotive MIPI A-PHY Sink IP (2-Lane)
The CL12912IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...
47
10.0
Automotive MIPI A-PHY Sink IP (2-Lane)
The CL12912IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...
48
10.0
Automotive MIPI A-PHY Source IP - 1-Lane
The CL12911IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...
49
10.0
Automotive MIPI A-PHY Source IP - 1-Lane
The CL12911IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...
50
8.0
IGAADCR13A, TSMC CLN55LP 12Bit 100MHz Pipelined ADC [1ch]
IGAADCR13A is a general-purpose analog to digital converter (ADC) with 12-bit resolution. This ADC is based on pipelined architecture and the sampling...