Design & Reuse
3868 IP
1
60.0
IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology
IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology...
2
60.0
TSMC CLN16FFGL+ HBM PHY IP
This datasheet describes GUC’s HBM (High Bandwidth Memory) PHY IP, which can be integrated with HBM memory controller to provide HBM functionality. Th...
3
60.0
TSMC CLN5FF HBM PHY IP
This datasheet describes GUC HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. Th...
4
60.0
TSMC CLN6FF/7FF Die-to-Die Interface PHY
IGAD2DX01A is a high speed die-to-die interface PHY which transmits data through INFO RDL channels. IGAD2DX01A contains 32 Tx lanes and 32 Rx lanes pe...
5
60.0
Multi-Die interLink (GLink 2.3) IP
GUC multi-die interLink (GLink) IP provides world’s best class solution for high-bandwidth, low-power, low-latency multi-channel interconnection in a ...
6
30.0
UFS Host Controller 4.1 IP
The UFS Host Controller Interface (UFSHCI) is a high-performance interface that connects to UniPro and M-PHY IP in mobile platforms. It provides comma...
7
40.0
Camera SLVS-EC 3.0 Receiver 10.0Gbps 8-Lane
* The CL12812M8RIP10000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL12812M...
8
25.0
Superscalar Out-of-Order Execution Multicore Cluster
AndesCore™ AX65 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on AndeStar™ V5 architectu...
9
35.0
Radiation-Hardened eFPGA
QuickLogic’s radiation-hardened eFPGA IP uses the company’s proven Australis eFPGA IP generation flow to provide customizable eFPGA IP optimized for s...
10
20.0
PCIe 4.0 PHY in TSMC(6nm,7nm,12nm,16nm)
M31 PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 4.0 IP suppo...
11
20.0
PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
M31 PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 5.0 IP suppo...
12
20.0
MIPI C-PHY/D-PHY Combo(5nm, 7nm, 12/16nm, 28nm, 40nm, 55nm)
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...
13
20.0
MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)
MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pi...
14
20.0
USB4 Gen3X2 and DP1.4 X4 PHY IP with Type-C connector support
M31 USB4 Gen3x2 transceiver IP provides a complete range of USB4 Gen3x2 host and peripheral applications up to 40Gbps. It is compliant with the PIPE5....
15
30.0
Camera SLVS-EC/MIPI D-PHY/sub-LVDS/CMOS1.8 combo Receiver 5.0G/2.5G/1Gbps/166MHz 8-Lane
* The CL12842M8RM3AM5AIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL1284...
16
30.0
Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
* The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams. A phase-locked clock is t...
17
30.0
Low jitter 4.96GHz to 5.6GHz PLL in TSMC N40
PMCC_PLL5GN40 is a PLL IP block which synthesizes low-jitter (<0.3ps RMS) 4.96GHz to 5.6GHz (5.28GHz typical) clock signals from the 620-700MHz refere...
18
30.0
PVT Sensor TSMC 40G
The PVT Sensor is an IP block which monitors chip Process, Voltage, and Temperature (PVT) providing a high accuracy measurement result. The sensor con...
19
10.0
UniPro 1.6 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
20
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
21
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
22
10.0
UniPro Controller 2.0 IP (host / device)
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
23
10.0
USB 3.2 Gen2/Gen1 PHY IP in TSMC(3nm, 5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps. It is compl...
24
20.0
Camera SLVS-EC 2.0 Receiver 5.0Gbps 8-Lane
* The CL12812M8RIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL12812M8RI...
25
5.0
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)
The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compr...
26
5.0
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compr...
27
5.0
32-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ A25MP 32-bit multicore CPU IP is based on AndeStar™ V5 architecture. It supports RISC-V standard ‘IMAC-FD’ extensions, Andes contributed DS...
28
5.0
M31 ADC / Temp. Sensor IP in 12nm, 14nm, 22nm Process
The M31 SAR ADC provides a rich portfolio with a resolution from 10 to 12-bit, maximum speed up to 2.5MSPS, and supports input types of single-ended o...
29
5.0
M31 Digital PLL IP in 3nm, 5nm, 6nm, 7nm, 12nm, 16nm, 22nm,28nm,40nm
M31 Digital PLL is a core-power only programmable phase-locked loop (PLL) for frequency synthesis. It supports multiple modes of operation for several...
30
5.0
M31 DisplayPort RX IP in 6/7nm, 22nm
M31 DisplayPort RX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort RX supp...
31
5.0
M31 eUSB2 PHY IP(2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 28nm)
Embedded USB2 (eUSB2) is a new generation specification proposed by USB Association that extends USB 2.0 specification and uses 1.2V/1.0V as the inter...
32
5.0
64-Bit 8-stage superscalar processor that supports RISC-V specification, including GCN
The 64-bit NX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit comp...
33
5.0
64-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 64-bit AX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit comp...
34
5.0
64-bit CPU Core with Level-2 Cache Controller
The 64-bit AX27L2 is a 5-stage processor that supports the latest RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit comp...
35
5.0
64-bit CPU with Modern RISC Architecture, MemBoost and PMA
The 64-bit AX27 is a 5-stage processor that supports the latest RISC-V specification, including "G" ("IMAFD") standard instructions, "C" 16-bit compre...
36
5.0
64-bit CPU with RISC-V Vector Extension
The 64-bit NX27V is a vector processor with 5-stage scalar pipeline that supports the latest RISC-V specification, including the IMAFD standard instru...
37
5.0
64-bit CPU with RISC-V Vector Extension
The 64-bit NX27V is a vector processor with 5-stage scalar pipeline that supports the latest RISC-V specification, including the IMAFD standard instru...
38
5.0
64-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ AX25MP 64-bit multicore CPU IP is based on AndeStar™ V5 architecture. It supports RISC-V standard 'IMAC-FD' extensions, Andes contributed D...
39
5.0
64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
AndesCore™ AX45MPV 64-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture. I...
40
5.0
DDR4/LPDDR4/LPDDR4X PHY
M31 LPDDR4X multi-PHY supports both LPDDR4 and LPDDR4X memory interfaces at speed up to 4267Mbps, making it an ideal solution for ASICS, ASSPs, SOC an...
41
5.0
Memory Compiler(12nm,16nm,22nm,28nm,40nm,55nm, 90nm, 115nm, 130nm, 150nm, 180nm)
M31 memory compilers are designed with high industrial standards to which provides the memory solutions for density, power, and performance optimizati...
42
5.0
General Purpose I/O (GPIO)(12nm,16nm,22nm, 28nm, 40nm, 55nm, 90nm, 110nm, 130nm, 150nm,152nm, 180nm)
GPIO is a general-purpose input/output unit that provides basic input/output functionalities. M31 provides silicon-proven GPIO libraries in a variety ...
43
5.0
Efficient 32-bit Processor with Custom Instructions
The new Andes Technology E8 CPU processor core targets Internet of Things (IoT) applications with the unique Andes Custom Extension™ (ACE) on a power-...
44
5.0
High-efficiency Low-power Processor
System-on-chip designs are proliferating to help OEMs automate functions such as smart lights, heating and cooling, wireless door locks, smoke, fire, ...
45
5.0
High-performance Processor for Real-time and Linux Applications
The Andes Technology N13 processor is a high performance CPU core architected for computation intensive applications running either on operating syste...
46
5.0
Highly-Configurable 32-bit Processor
The AndesCore N9 Family is intended for deeply embedded applications that require optimal interrupt response features, including wireless networking a...
47
5.0
MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...
48
5.0
MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...
49
5.0
RISC-V CPU IP With ISO 26262 Full Compliance
AndesCore™ N25F is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of delivering high per-...
50
5.0
DisplayPort TX IP for high-bandwidth applications (6nm, 12nm, 28nm)
M31 DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort TX supp...