1 0.0

SFA 350A - Sondrel Quad-channel ADAS Platform The SFA 350A platform has been specifically designed for ADAS (Advanced Driver Assistance Systems) that are used to support driverless or automotive v...

2 200.0

Post-Quantum Cryptography - xQlave® PQC ML-KEM (Kyber) In a world where advances in quantum computing threaten traditional cryptographic systems, Xiphera’s xQlave® ML-KEM (Kyber) Key Encapsulation Mechanis...

3 105.0

CME IoT platform Sensor-Mate (sensing node)Long distance wireless communication (920MHz)Sensor-Gateway (Aggregator)920MHz wireless module (CM Engineering proprietary)G...

4 104.0

LPDDR5X, LPDDR5, LPDDR4X, LPDDR4 Combo PHY & Controller The INNOSILICON™ LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller. It is fully compliant with the JEDEC standard. Optimized for low-power a...

5 100.0

MACsec - Extreme-speed - Security Protocol MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera's comprehensive MACsec solution portfolio safeguards th...

6 100.0

PCIe 5.0 PHY & Controller The Innosilicon Gen1/2/3/4/5 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, h...

7 100.0

Post-Quantum Cryptography - nQrux® Secure Boot - Quantum-Secure Authenticated Boot (PQC) nQrux® Secure Boot enhances system security by enabling quantum-secure authenticated boot, crucial for verifying the authenticity and integrity of bin...

8 100.0

Post-Quantum Cryptography - xQlave® PQC ML-DSA (Dilithium) The xQlave® ML-DSA (Dilithium) Digital Signature Algorithm IP core secures critical infrastructures and operations against the threat of quantum compu...

9 60.0

UCIe Chiplet PHY & Controller INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...

10 51.0

TLS 1.3 - Security Protocol Transport Layer Security (TLS) is a cryptographic protocol used for building a secure connection between a client and a server over the Internet. A ha...

11 51.0

True Random Number Generator (TRNG) The TRNG IP core establishes a benchmark for hardware-based security in cryptographic systems, by generating high-entropy, true random numbers essenti...

12 50.0

MAXVY Technologies MAXVY is a fast growing fabless semiconductor company which is currently engaged in the fields of RTL design and Verification IP Solutions. We offe...

13 50.0

AES - GCM - Extreme-speed variant Xiphera's AES symmetric encryption IP cores ensure robust encryption and decryption, providing data confidentiality and integrity with the Advanced En...

14 50.0

IPsec - Security Protocol IPsec (Internet Protocol Security) is a widely implemented protocol to secure communications across the Internet. Xiphera’s IPsec core enhances secure...

15 48.0

nQrux® Crypto Module Xiphera’s nQrux® Crypto Module IP core provides a comprehensive security platform that allows for customisation of top-notch cryptographic services, s...

16 43.0

Elliptic Curve Cryptography (ECC) Accelerator The high-speed ECC Accelerator reaches to more than a thousand operations per second in a modern FPGA or ASIC. Furthermore, it covers all NIST P curve...

17 30.0

GDDR7 PHY & Controller The INNOSILICON™ GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode. In PAM3 mode, each b...

18 25.0

2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver The SVRPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture ...

19 25.0

HBM4, HBM3E PHY & Controller INNOSILICON™ HBM4/3E IP is fully compliant with the JEDEC standard for HBM3E and the preliminary specification for HBM4. The IP includes a customizabl...

20 25.0

DDR5, DDR4 Combo PHY & Controller The INNOSILICON DDR IPTM Mixed-Signal DDR5/4 Combo PHY s provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDR...

21 15.0

2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture of t...

22 15.0

GDDR6X, GDDR6 Combo PHY & Controller The INNOSILICON™ GDDR6X/6 PHY is fully compliant with the JEDEC GDDR6X/6 standard, supporting data rates of up to 20 Gbps per pin for PAM2 GDDR6 mode ...

23 15.0

High Performance Second Generation Extended MIPI CSI2 Receiver Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth betwe...

24 15.0

MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations. It complies with MIPI® CSI2 V2.0 and DPHY1.2 spec...

25 15.0

Multi-Video-Source Multiplexing Serial Video Transmitter for MIPI CSI2 The SVT-CS4AP2 supports MIPI CSI2 over MIPI D-PHY. It allows mutilplexing of up to 10 video sources into a CSI2 output stream...

26 15.0

Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth betwe...

27 13.0

Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output This IP multiplexes inputs from up to 4 CSI2 cameras, each with up to 4 data lanes, to a single CSI2 output stream, with up to 4 lanes. It comprises o...

28 10.0

MIPI DSI-2 Transmitter Interface IP MIPI DSI-2 (Display Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile dev...

29 8.0

MIPI I3C Verification IP with IBI feature enabled ...

30 8.0

Universal Chiplet Interconnect Express (UCIe) Verification IP MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of you...

31 8.0

SureFIT Custom SRAM Design Service Provides a SRAM design service customised to customer specification. SureFIT deploys silicon proven and patented low-power design techniques with powe...

32 7.0

Hardware NLM (Non-Local-Mean) Video Noise Reduction IP core NLM (Non Local Mean) is a noise reduction algorithm wherein the value of each pixel is determined a rectangle of pixels around that pixel (a “center p...

33 7.0

Ultra Low Power Embedded SRAM on TSMC 16FFC PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

34 7.0

PowerMiser Ultra Low Power Embedded SRAM SE 28FDS PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

35 7.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 22ULL PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

36 7.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 28HPC+ PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

37 7.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 40ULP PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

38 7.0

Standard cell cryogenic recharacterisation service for GF 22FDX to 4K operating temp Provides a cryogenic recharacterisation service for standard cells to operate down to 4K...

39 6.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 130 PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

40 6.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 180 PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

41 6.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 55ULP PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

42 6.0

PowerMiser Ultra Low Power Embedded SRAM TSMC 90 PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance c...

43 6.0

MultiPort Low Voltage Register File MiniMiser™ is a tuneable multi-port register file architecture that can support both low power and high-performance applications. Its unique implement...

44 6.0

MultiPort Low Voltage Register File MiniMiser™ is a tuneable multi-port register file architecture that can support both low power and high-performance applications. Its unique implement...

45 6.0

MultiPort Low Voltage Register File MiniMiser™ is a tuneable multi-port register file architecture that can support both low power and high-performance applications. Its unique implement...

46 6.0

MultiPort Low Voltage Register File MiniMiser™ is a tuneable multi-port register file architecture that can support both low power and high-performance applications. Its unique implement...

47 6.0

MultiPort Low Voltage Register File MiniMiser™ is a tuneable multi-port register file architecture that can support both low power and high-performance applications. Its unique implement...

48 5.0

MIPI I3C Master RISC-V based subsystem RISC-V based MAXVY MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a ...

49 5.0

MIPI SPMI Host Controller The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...

50 5.0

MIPI SPMI Target Controller The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...