Design & Reuse
30 IP
1
2.0
K-Best (2X2) MIMO Decoder
The K-best decoder is part of the MIMO decoder. The MIMO Decoder accepts two independent input streams, and the channel estimation matrix. The inputs ...
2
2.0
K-Best (4X4) MIMO Decoder
The K-best decoder is part of the MIMO decoder. The MIMO Decoder accepts two independent input streams, and the channel estimation matrix. The inputs ...
3
2.0
K-Best MIMO Decoder
The K-best decoder is part of the MIMO decoder. The MIMO Decoder accepts two independent input streams, and the channel estimation matrix. The inputs ...
4
2.0
BCH Encoder/Decoder
The binary BCH decoder has four main functional blocks along with memory blocks: 1. Syndrome calculation block: identifies the presence of errors in ...
5
2.0
CCSDS LDPC
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6
2.0
LDPC Decoder for DVB-C2
In Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes c...
7
2.0
LDPC Decoder for DVB-T2/T2-Lite
In Digital video broadcasting for terrestrial broadcasting systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Chec...
8
2.0
LDPC Decoder for IS-GPS-800D Applications
The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parity Check (LDPC) Forwar...
9
2.0
Reed Solomon Encoder/Decoder
- The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the input message in order ...
10
2.0
AES IP Core
Encryption and Decryption are fed with an input of 128 bits length and an initial key of one of the supported key lengths (128, 192 and 256). The AES...
11
2.0
FFT/IFFT Engine
The FFT/IFFT engine is a parametrized FFT stage used as the main building block for FFT/IFFT/DFT blocks....
12
2.0
Zigbee Transceiver PHY
The modulation and spreading functions for the O-QPSK PHYs are processed through 3 steps. First, each 4 bits are gathered to represent 1 symbol which ...
13
2.0
MIMO Sphere Decoder
The VK-402 searches only within a fixed number of lattice points, where the number of considered lattice points decreases as we descend from level N. ...
14
2.0
Viterbi Decoder
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors...
15
2.0
Flash Memory LDPC
LDPC corrects errors caused by flash storage failure mechanisms. The data is encoded while writing into the storage devices and it is decoded while re...
16
2.0
ASIP-1
The programmable filter engine (PFE) is a configurable and expandable IP that implements FIR, decimation, interpolation and IIR filtering functions. T...
17
2.0
ASIP-2
The FFT/IFFT/DCT engine is an application specific instruction set processor (ASIP) optimized for the implementation of Fourier and cosine transforms,...
18
2.0
LTE Lite
The design is a CAT 0/1 LTE Lite PHY, the demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system...
19
2.0
LTE Rx Bit Chain
In the downlink transmission, the physical downlink shared channel (PDSCH) carries the user data (Transport block). The modulation format of PDSCH cha...
20
2.0
LTE Turbo decoder
This block is suitable for 3GPP Long Term Evolution (LTE) applications compatible with the 3GPP Technical Specification. The LTE Release-8 Turbo code ...
21
2.0
DVB-C Demodulator
The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC). The system has an internal state machine...
22
2.0
DVB-T2 Demodulator
In the DVB-T2 transmission, the Physical Layer Pipes (PLPs) carries the MPEG-2 Transport Streams (TSs). The system input/inputs may be one or more MP...
23
1.0
LDPC Decoder for 802.11
This is an LDPC decoder compliant with the IEEE 802.11 n/ac/ax standards. It supports high throughput,...
24
1.0
LDPC Decoder for DVB-S2
In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Dens...
25
1.0
HomePlug Turbo Decoder
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer. There are three separate processing chains: A) H...
26
1.0
Non-binary LDPC Decoder
A powerful Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems. Low-Density Parity-Check (LDPC) codes are ...
27
1.0
AR4JA LDPC Decoder
AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3 and 3/4). To obtain hi...
28
0.0
Wasiela - complete System and RTL design services
Wasiela provides complete System and RTL design services that Include: Digital Design and Verification Custom Communication System Design In...
29
0.0
NavIC BCH Decoder
The Wasiela NA VIC BCH decoder is developed for satellite navigation applications....
30
0.0
NR-5G Polar Encoder /Decoder
The Wasiela NR-5G Polar encoder/decoder is developed for 5G new radio. Fully compliant with 3GPP TS 38.212: Sections 5.2.1, 5.3.1, 5.4.1 and 5.5...