Design & Reuse
Catalog of SIP Cores
System on Chip design resources
3735 IP
51
11.0
NVM OTP NeoBit in HJTC (180nm, 160nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
52
11.0
NVM OTP NeoBit in Huali (55nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
53
11.0
NVM OTP NeoBit in JSC (130nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
54
11.0
NVM OTP NeoBit in MagnaChip (350nm, 180nm, 150nm, 130nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
55
11.0
NVM OTP NeoBit in Maxchip (180nm, 160nm, 150nm, 110nm, 90nm, 80nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
56
11.0
NVM OTP NeoBit in NEXCHIP (150nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
57
11.0
NVM OTP NeoBit in Samsung (130nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
58
11.0
NVM OTP NeoBit in SHARP (180nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
59
11.0
NVM OTP NeoBit in Silterra (180nm, 160nm, 130nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
60
11.0
NVM OTP NeoBit in SKHYNIX (180nm, 130nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
61
11.0
NVM OTP NeoBit in SMIC (350nm, 180nm, 160nm, 130nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
62
11.0
NVM OTP NeoBit in TSMC (350nm, 250nm, 180nm, 160nm, 130nm, 110nm, 90nm, 80nm, 55nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
63
11.0
NVM OTP NeoBit in UMC (180nm, 160nm, 130nm, 110nm, 80nm, 55nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
64
11.0
NVM OTP NeoBit in Vanguard (350nm, 250nm, 180nm, 160nm, 150nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
65
11.0
NVM OTP NeoBit in X-FAB (250nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
66
0.0
NeoPUF - an ideal security solution for IoT
NeoPUF is a hardware security technology based on the physical unclonable variations occurring in silicon manufacturing process. The underlying benefi...
67
0.0
NVM EEPROM NeoEE in DBHitek(180nm, 90nm)
eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...
68
130.0
LPDDR6, LPDDR5X Combo PHY & Controller
INNOSILICON™ introduces its LPDDR6/5X PHY and Controller IP, purpose-built for the AI era’s high-performance chip design needs. This solution is fully...
69
100.0
1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
eTopus designs ultra-high speed mixed-signal semiconductor IP solutions for high-performance computing and data center applications. Our 1-56/112Gbps ...
70
100.0
400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
...
71
100.0
56G Serdes in 7nm bundled with PCie Gen 5 controller IP
New IP for value conscious designers....
72
100.0
PCIe 5.0 PHY & Controller
The Innosilicon Gen1/2/3/4/5 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, h...
73
100.0
PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
Multiprotocol low latency, low power SERDES IP....
74
100.0
Complete USB Type-C Power Delivery PHY, RTL, and Software
The OTI9108 is a complete single transceiver front end for data USB PD Type-C (baseband) communications. It has a register interface which, with an MP...
75
100.0
LPDDR5X, LPDDR5, LPDDR4X, LPDDR4 Combo PHY & Controller
The INNOSILICON™ LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller. It is fully compliant with the JEDEC standard. Optimized for low-power a...
76
80.0
GDDR7 PHY & Controller
The INNOSILICON™ GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode. In PAM3 mode, each b...
77
70.0
DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
78
70.0
LPDDR6/5X/5/4X/4 combo PHY at Samsung SF5A
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
79
70.0
LPDDR6/5X/5/4X/4 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
80
60.0
UCIe Chiplet PHY & Controller
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
81
60.0
IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology
IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology...
82
50.0
512x8 Bits OTP (One-Time Programmable) IP, TSM- 12FFC 0.8V/1.8V Process
The ATO00512X8TS012FFC8EA is organized as 512 bits by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in 12nmFFC stand...
83
50.0
High Bandwidth Out-of-Order RISC-V CPU IP Core
...
84
50.0
High Bandwidth Out-of-Order RISC-V CPU IP Core
...
85
50.0
LPDDR5/4x/4 combo PHY on 14nm, 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
86
50.0
Nuclei NA900: ASIL-B/D compliant 32/64-bit safety-certified 9-stage-pipeline processor for automotive and safety-critical applications
As the world’s first RISC-V CPU IP fully compliant with ISO 26262 ASIL-B/D certification, it is a dual-issue, in order execution core engineered for ...
87
46.0
32Gbps, 31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions reg...
88
46.0
32Gbps, 7/15 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7 or 15 order, up to 32Gbps. Error count is accurate: no double counts or omission...
89
46.0
32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7, 15 or 31 order, up to 32Gbps. Error count is accurate: no double counts or omis...
90
40.0
LPDDR5X/5/4X/4 combo PHY at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
91
40.0
LPDDR5X/5/4X/4 PHY for 16nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
92
40.0
LPDDR5X/5/4X/4 PHY IP for 12nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
93
30.0
4-/8-bit mixed-precision NPU IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
94
30.0
UCIe Die-to-Die Chiplet Controller
Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innova...
95
30.0
UFS Host Controller 4.1 IP
The UFS Host Controller Interface (UFSHCI) is a high-performance interface that connects to UniPro and M-PHY IP in mobile platforms. It provides comma...
96
30.0
High speed NoC (Network On-Chip) Interconnect IP
OPENEDGES is the only total memory system IP company providing both memory controller and on-chip interconnect. OIC is the ORBIT high-speed On-chip In...
97
30.0
Highly scalable inference NPU IP for next-gen AI applications
OPENEDGES, the total memory subsystem IP provider, introduces ENLIGHT Pro, a state-of-the-art inference neural processing unit (NPU) IP that outperfor...
98
30.0
RISC-V Tensor Unit
The bulk of computations in Large Language Models (LLMs) is in fully-connected layers that can be efficiently implemented as matrix multiplication. Th...
99
30.0
All in one solution for AI in RISC-V
...
100
30.0
Nuclei N900(SMP): 32-bit high-efficiency 9-stage-pipeline processor with DSP/FPU capable for embedded and real-time applications
32-bit high-performance RISC-V core, belonging to Nuclei 900 Series, optimized for high-performance embedded scenarios without MMU. Comparable to ARM ...