Design & Reuse
Catalog of SIP Cores
System on Chip design resources
3938 IP
501
10.0
GDDR6 PHY IP for 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
502
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY (in production)...
503
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
504
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
505
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
506
10.0
Gigabit Ethernet PHY (Modification Right)
Gigabit Ethernet PHY Modification Right (in production)...
507
10.0
RISC-V Vector Unit
A Vector Unit is composed of several 'vector cores', roughly equivalent to a GPU core, that perform multiple calculations in parallel. Each vector cor...
508
10.0
4Kx16 Bits OTP (One-Time Programmable) IP, UM- 110 nm 1.2V/3.3V L110AE Process
The AT4K16U110MAE0DA is organized as a 4K-bits by 16 one-time programmable memory. This is a kind of non-volatile memory fabricated in UM- L110AE proc...
509
10.0
4Kx32 Bits OTP (One-Time Programmable) IP, TSM- 40nm ULP 1.1V/2.5V Process
The AT4K32T40ULP7ZC is organized as 4K-bits by 32 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSM- 40nm ULP stand...
510
10.0
4Kx8 Bits OTP (One-Time Programmable) IP, GLOBA-FOUNDR---® 22nm FDX 0.8V/1.8V Process
The AT4K8G22FDX0AA is organized as a 4K-bits by 8 one-time programmable memory. This is a kind of non-volatile memory fabricated in GLOBA-FOUNDR---® ...
511
10.0
8Kx8 Bits OTP (One-Time Programmable) IP, VI- 0.15µm 1.8V/5V BCD GIII Process
The AT8K8V150BCD0DB is organized as an 8K-bit by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in VI- 0.15μm BCD GII...
512
10.0
OneStar Technology Engineering Services
OneStar Technology is a professional Silicon Intellectual Property (SIP) solution provider, while also offers Electronic Design Automation (EDA), Comp...
513
10.0
UniPro 1.6 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
514
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
515
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
516
10.0
UniPro Controller 2.0 IP (host / device)
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
517
10.0
USB 3.2 Gen2/Gen1 PHY IP in TSMC(3nm, 5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps. It is compl...
518
10.0
1x64 Bits OTP (One-Time Programmable) IP, Globa-Foundr--- 22nmFDX 0.8V/1.8V Process
The AT1X64G22FDX0AA is organized as a 1 by 64 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in Globa-Foundr--- 22nm FD...
519
8.0
10/100 Base-TX Fast Ethernet PHY; SMIC 40nm LL
SP-10_100_Ethernet-S40LL is a single-port DSP-based Fast Ethernet Transceiver. It contains all the active circuitry required to convert data stream to...
520
8.0
10/100 Ethernet PHY for TSMC 22nm ULP
10 100ETHERNET-T22ULP18 is a single-port DSP-based Fast Ethernet Transceiver. It contains all the ac?tive circuitry required to convert data stream to...
521
8.0
10/100 Ethernet PHY, TSMC 28nm HPC+
-10 100ETHERNET-T28HPCP18 is a single-port DSP-based Fast Ethernet Transceiver. It contains all the ac?tive circuitry required to convert data stream ...
522
8.0
Single port 10/100 Fast Ethernet Transceiver - TSMC12nm FFC
SP-10 100ETHERNET-T12FFC is a single-port DSP-based Fast Ethernet Transceiver. It contains all the active circuitry required to convert data stream t...
523
6.0
2-ch 16-bit stereo Audio ADC
...
524
6.0
2-ch 16-bit stereo Audio ADC
...
525
6.0
2-ch 24-bit 192KSPS Audio DAC
...
526
6.0
2-ch 24-bit 192KSPS Audio DAC
...
527
6.0
2-ch 24-bit 192KSPS Audio DAC; TSMC 40nm LP
...
528
6.0
10-bit dual-port 30MHz ~ 85MHz LVDS Tx;
...
529
6.0
10/100 Base-TX Fast Ethernet PHY; TSMC 55nm GP
...
530
6.0
24-bit 192KSPS Audio DAC
...
531
6.0
24-bit 192KSPS Audio DAC;
...
532
6.0
16-bit 48KSPS stereo Audio ADC
...
533
6.0
16-bit 48KSPS stereo Audio ADC;
...
534
6.0
Technology Development Services
CSEM – Pioneering Ultra-Low Power ASIC and SoC Innovation CSEM is a Swiss public-private, non-profit technology innovation center with over 40 year...
535
6.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
536
6.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
537
6.0
MIPI Rx D-PHY
...
538
6.0
LPDDR4/DDR4/DDR3 PHY - TSMC 22nmULL
SP-LPD4/D43_PHY16BIT-T22ULL is designed for DRAM controller to connect to the LPDDR4/DDR4/3 DRAM memory device. It contains a DDR PHY Control Unit(DPC...
539
6.0
USB 2.0 PHY; SMIC 40nm LL
...
540
6.0
USB 2.0 PHY; SMIC 55nm LL
...
541
6.0
LVDS 10 bits dual port transmitter
...
542
5.0
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)
The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compr...
543
5.0
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compr...
544
5.0
32-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ A25MP 32-bit multicore CPU IP is based on AndeStar™ V5 architecture. It supports RISC-V standard ‘IMAC-FD’ extensions, Andes contributed DS...
545
5.0
M31 ADC / Temp. Sensor IP in 12nm, 14nm, 22nm Process
The M31 SAR ADC provides a rich portfolio with a resolution from 10 to 12-bit, maximum speed up to 2.5MSPS, and supports input types of single-ended o...
546
5.0
M31 Digital PLL IP in 3nm, 5nm, 6nm, 7nm, 12nm, 16nm, 22nm,28nm,40nm
M31 Digital PLL is a core-power only programmable phase-locked loop (PLL) for frequency synthesis. It supports multiple modes of operation for several...
547
5.0
M31 DisplayPort RX IP in 6/7nm, 22nm
M31 DisplayPort RX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort RX supp...
548
5.0
M31 eUSB2 PHY IP(2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 28nm)
Embedded USB2 (eUSB2) is a new generation specification proposed by USB Association that extends USB 2.0 specification and uses 1.2V/1.0V as the inter...
549
5.0
64-Bit 8-stage superscalar processor that supports RISC-V specification, including GCN
The 64-bit NX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit comp...
550
5.0
64-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 64-bit AX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit comp...