Design & Reuse
5923 IP
5851
0.0
Automotive MIPI D-PHY Universal IP in TSMC 28HPC+
The AUTO-MXL-DPHY-UNIV-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specific...
5852
0.0
Automotive MIPI D-PHY Universal IP in UMC 28HPC+
The AUTO-MXL-DPHY-UNIV-U-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificatio...
5853
0.0
Automotive MIPI D-PHY/LVDS Combo TX (Transmitter) in Samsung 28FDSOI
The AUTO-MXL-LVDS-DPHY-DSI-TX-SS-028FDSOI is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer sup...
5854
0.0
Automotive-Compliant Synopsys UCIe Controller IP
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
5855
0.0
JVC 2D3D Conversion Soft IP for Android - Convert 2D Image into 3D stereoscopic image in real-time
JVC 2D3D Conversion Soft IP for Android mobile and tablet....
5856
0.0
JVC 3D Frame Rate Converter IP - 3D-FRC convert 50/60fps video to blur-less and judder-less 100/120fps
JVC s 3D-FRC IP is now available for licensing. It offers frame rate conversion and 3D decoding with high performance....
5857
0.0
JVC De-interlacer for Mobile IP - High quality and small gate count De-interlacer for mobile
JVC KENWOOD s De-interlacer IP, which is already used in its products, is now available for licensing. Because it has been already proven in the marke...
5858
0.0
JVC Enhancer - JVC Object-Based Gloss Enhancer
JVC s Object-Based Gloss Enhancer IP, which is already used in its products, is now available for licensing. Because it has been already proven in the...
5859
0.0
JVC Frame Rate Converter (FRC) IP - FRC convert 50/60fps video to blur-less and judder-less 100/120fps.
JVC s FRC IP is now available for licensing. It offers frame rate conversion with high performance....
5860
0.0
JVC Smart LVDS Interface IP - JVC SmartLVDS IP reduce cost dramatically for middle to low-end LCD TV.
JVC Kenwood is a leading company for the art of televisions, digital cameras and camcorders in the world. Now JVC is providing their leading edges ima...
5861
0.0
JVC_2D to 3D_conversion_IP - JVC 2D3D Conversion IP for TV, projector, mobile, photo frame
JVC Kenwood is a leading company for the art of televisions, digital cameras and camcorders in the world. Now JVC is providing their leading edges ima...
5862
0.0
JVC_3D Noise Reduction_IP - JVC Motion-estimated 3D Noise Reduction IP core
JVC Kenwood is a leading company for the art of televisions, digital cameras and camcorders in the world. Now JVC is providing their leading edges ima...
5863
0.0
JVC_4K Adoptive Scaler + Super Resolution - Convert Full-HD to High quality 4k2k with super resolution technology
JVC s 4k2k Super Resolution IP is now available for licensing. It offers dramatically less jaggy and Full-HD to 4k2k up-conversion with high performan...
5864
0.0
JVC_NLC_IP (near loss less compression) - JVC Near Loss-less Compression (NLC) IP core
JVC Kenwood is a leading company for the art of televisions, digital cameras and camcorders in the world. Now JVC is providing their leading edges ima...
5865
0.0
LVDS Tx and OpenLDI Tx (Automotive IP)
InPsytech Inc., an Automotive interface IP solution provider, introduces its latest Automotive High-Speed Interface IP Series, designed to meet the ri...
5866
0.0
LVDS TX+ (Transmitter) in UMC 40LP
The MXL-LVDS-SR-TX+ is a high performance 4-channel LVDS transmitter implemented using digital CMOS technology. With a maximum transmit clock frequenc...
5867
0.0
DVinsight - Correct by construction SV UVM code with a smart editor
DVinsight™ is a smart editor for creation of Universal Verification Methodology (UVM) based System Verilog (SV) Design Verification (DV) code.DV...
5868
0.0
NVM OTP in GF (30nm, 65nm, 55nm, 40nm, 28nm, 22nm, 12nm)
Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...
5869
0.0
NVM OTP in TSMC N5A for Automotive
One Time Programmable (OTP) Non-Volatile Memory (NVM) IP solution, based on XHF architecture, is designed to meet the challenges of advanced FinFET de...
5870
0.0
NVMe Verification IP
Non Volatile Memory Express, also known as NVMe is an interface specification built for accessing Solid State Drive (SSD) over PCIe. NVMe has revoluti...
5871
0.0
PVT - Process, Voltage, and Temperature Monitor with Interrupt 7nm/6nm
The ODT-PVT-ULP-001C-7 is an ultra-low power temperature, voltage and process monitor designed in a 7nm/6nm CMOS process. This IP operates over the en...
5872
0.0
SWI3S Manager core IP
Arasan’s SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer the...
5873
0.0
SWI3S Peripheral core IP
Arasan’s SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer ...
5874
0.0
PWM to Class D Amplifier Power Stage, SMIC 0.13um
The AR35S13A is a highly efficient H-BTL audio output driver IP for Class-D amplifier application. The IP is capable of providing 0.1% THD+N performan...
5875
0.0
AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash...
5876
0.0
AXI Bus Display Controller
The Digital Blocks DB9000AXI3 Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconnect to...
5877
0.0
AXI Interconnect Fabric
The AXI Interconnect provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Masters. AXI defines 5...
5878
0.0
AXI Interface Core
Rambus’s AXI Interface Core is designed for use in applications requiring ARM’s Advanced eXtensible Interface (AXI). The core accepts write and rea...
5879
0.0
AXI Multilayer Interconnect
The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The AXI fabric ...
5880
0.0
AXI Subsystem
The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces...
5881
0.0
AXI to AHB Lite Bus Bridge
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...
5882
0.0
AXI to APB Bridge
The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI bus. The highly con...
5883
0.0
AXI to APB Bus Bridge
The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one ...
5884
0.0
AXI4 Memory Map to AXI4-Stream Bridge
Digital Blocks DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the address to ...
5885
0.0
AXI4 to/from AXI4-Stream Scatter-Gather DMA
The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the ho...
5886
0.0
AXI4 to/from Stream DMA
The AXI4-DMA IP core implements a Direct Memory Access (DMA) engine that efficiently moves data between AXI4-Stream peripherals and a memory-mapped AX...
5887
0.0
AXI64 5 Port SRAM Controller
The AXI 5-Master component SRAM Controller provides 5 AXI 64-bit Master components with low-wait-state access to a single internal 64-bit SRAM resourc...
5888
0.0
CXL Controller IP
The Wolley Compute Express Link® (CXL®) 3.1 controller is a highly-configurable design for ASIC and FPGA implementations. It maintains backward compat...
5889
0.0
CYB-SM3 Cryptographic Hash Function
SM3 is a hash algorithm initially published by the Office of State Commercial Cryptography Administration (OSCCA) of SCA in 2010, then as a China indu...
5890
0.0
CYB-SM4 Block Cipher Algorithm
SM4 (former name “SMS4”) is a cryptographic standard published by the Office of State Commercial Cryptography Administration (OSCCA) of SCA as an indu...
5891
0.0
Hybrid Memory Cube Verification IP
Atria Logic Hybrid Memory Cube verification IP is a reusable, configurable verification component developed using SystemVerilog. The IP offers an easy...
5892
0.0
Synchronous UART
...
5893
0.0
Synopsys 112G Ethernet PHY IP for TSMC N6
The Synopsys 112G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
5894
0.0
Synopsys 112G PHY for TSMC N7
Synopsys IP Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high perfor...
5895
0.0
Synopsys 224G Ethernet PHY IP for TSMC N3P
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
5896
0.0
Synopsys 32G PHY NCS for TSMC N5
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...
5897
0.0
Synopsys Auto-Grade MIPI D-PHY Tx for TSMC N7
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
5898
0.0
Synopsys DDR5 MRDIMM2 PHY IP for TSMC N3P
The Synopsys DDR5 MRDIMM2 PHY IP is part of a complete IP solution including PHY and Controller enabling ASIC, Application-specific standard products ...
5899
0.0
Synopsys High Speed Ethernet PCS IP up to 200G
The Synopsys Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a complete set of featu...
5900
0.0
Synopsys High-Speed Test IO in TSMC N3P
AI and HPC are transitioning to chiplet-based designs to overcome scaling limits of monolithic SoCs and achieve superior performance. While heterogene...