Design & Reuse
4956 IP
151
0.0
MIPI D-PHY TSMC 28nm HPM
The Arasan’s MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.1. It supports the MIPI® Camera Serial Inte...
152
0.0
MIPI D-PHY TSMC 40LP
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
153
0.0
MIPI D-PHY V1.2@2.5GHz Tx only
Arasan has the industry’s broadest portfolio of foundry and process technology support for MIPI D-PHY in the industry. The MIPI D-PHY analog IP is ava...
154
0.0
MIPI DSI-2 Receiver Controller v2.0
Arasan’s Display Host and DSI device controllers are built on existing MIPI Alliance standards by adopting pixel formats, controlling pins and comma...
155
0.0
MIPI DSI-2 Transmit Controller v2.0
Arasan’s Display Host and DSI device controllers are built on existing MIPI Alliance standards by adopting pixel formats, controlling pins and comma...
156
0.0
MIPI DSI-2 with VESA DSC
Arasan’s Total IP Solution for MIPI Display Serial Interface (DSI-2) with VESA DSC IP provides both device and host functionality along with VESA DSC ...
157
0.0
MIPI M-PHY Designed For TSMC 28nm
ACS-AIP-MPHY-28HPM MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A...
158
0.0
MIPI Soundwire PHY
The physical layer block implements all the line-side functions such as NRZI encoding & decoding, bus clash detection, data line buffer enable/disable...
159
0.0
MIPI SPMI 2.0 Device IP
Arasan’s SPMI Device IP (Configurable Controller Cores) implements MIPI SPMI2.0 protocols. It is designed to be configured as a SPMI Host, SPMI Device...
160
0.0
MIPI SPMI 2.0 Host IP
Arasan’s SPMI Host IP (Configurable Controller Cores) implements MIPI SPMI2.0 protocols. It is designed to be configured as a SPMI Host, SPMI Device C...
161
0.0
Globalfoundries 12nm MIPI D-PHY Rx only V1.2@2.5GHz
Arasan Chip Systems standalone MIPI D-PHY(SM) Recieve (Rx) only for Globalfoundries 12nm FinFET process nodes. Arasan's standalone D-PHY Rx only for...
162
0.0
Globalfoundries 12nm MIPI D-PHY Tx only V1.2@2.5GHz
Arasan Chip Systems standalone MIPI D-PHY(SM) Transmit only for Globalfoundries 12nm FinFET process nodes. Arasan's standalone D-PHY Tx only for Glo...
163
0.0
Globalfoundries 22nm MIPI D-PHY Rx only V1.2@2.5GHz
Arasan Chip Systems standalone MIPI D-PHY(SM) Recieve (Rx) only for Globalfoundries 22nm FinFET process nodes. Arasan's standalone D-PHY Rx only for...
164
0.0
Globalfoundries 22nm MIPI D-PHY Rx only V1.1@1.5GHz
Arasan 2nd Generation MIPI D-PHY v1.1 Rx IP supporting speeds of up to 1.5 Gbps on GF 22nm process technology for SoC designs. Arasan’s D-PHY IP is av...
165
0.0
Globalfoundries 22nm MIPI D-PHY Tx only V1.2@2.5GHz
Arasan Chip Systems standalone MIPI D-PHY(SM) Transmit only for Globalfoundries 22nm FinFET process nodes. Arasan's standalone D-PHY Tx only for Glo...
166
0.0
Globalfoundries 22nm MIPI D-PHY Tx only V1.1@1.5GHz
Arasan 2nd Generation MIPI D-PHY v1.1 Tx IP supporting speeds of up to 1.5 Gbps on GF 22nm process technology for SoC designs. Arasan’s D-PHY IP is av...
167
0.0
Globalfoundries 22nm MIPI D-PHY Universal Tx-Rx V1.1@1.5GHz
Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on GF 22nm process technology for SoC designs. Arasan’s D-PHY IP is avail...
168
0.0
Globalfoundries 22nm MIPI D-PHY Universal Tx-Rx V1.2 @ 2.5GHz
Arasan Chip Systems announces the immediate availability of its MIPI D-PHY(SM) Globalfoundries 22nm FinFET process nodes. Arasan's D-PHY Global Foun...
169
0.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF PLUS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
170
0.0
ONFI 2.3 NAND Flash Controller
The Arasan ONFI 2.3 NAND Flash Controller IP Core is a full featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA developm...
171
0.0
Arasan Chip Systems - SoC Design Services
Arasan Chip Systems is a leading provider of Total IP solutions for mobile storage and connectivity applications. Arasan’s high-quality, silicon-pr...
172
0.0
USB 2.0 OTG Dual Role Device
The Arasan USB 2.0 OTG DRD IP Core is compliant with the OTG Supplement Rev. 1.0a. The USB 2.0 OTG DRD core supports the Host Controller, Device Contr...
173
0.0
USB 2.0 PHY IBM 180
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
174
0.0
USB 2.0 PHY TSMC 40G
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
175
0.0
USB 3.0 Device Upgrade IP Core
The USB 3.0 Device Upgrade IP enables designers in the PC, mobile, consumer and communication markets to bring significant power and performance enhan...
176
0.0
Quad SPI Master IP
Arasan Chip Systems Quad SPI (QSPI) master core is easy to use, simple to work with, quick to operate, and reliable under all conditions. It supports ...
177
0.0
SWI3S Manager core IP
Arasan’s SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer the...
178
0.0
SWI3S Peripheral core IP
Arasan’s SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer ...
179
70.0
Image Signal Procesing, Real-time Pixel Processor Automotive
Dream Chips Real-time Pixel Processor (RPP) is a scalable and configurable High Dynamic Range (HDR) capable image signal processor (ISP), developed fo...
180
70.0
ISP, Image Signal Processing, Real-time Pixel Processor for Automotive
Dream Chip’s Real-time Pixel Processor (RPP) is a scalable and configurable High Dynamic Range (HDR) capable image signal processor (ISP), develo?ped ...
181
20.0
JESD204C
The JESD204C controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C.1 serial interface standard targeting both ...
182
15.0
JESD204B
The JESD204B controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204B.01 serial interface standard targeting both...
183
10.0
UALink PCS
The Chip Interfaces UA Link PCS IP Core is a high-performance, silicon-agnostic and fully compliant Physical Coding Sublayer (PCS) implementation of U...
184
10.0
UCIe D2D Adapter
The D2D Adapter for UCIe is a scalable adapter layer between one or more protocol components and the UCIe PHY, which ensures efficient data transfer a...
185
10.0
eCPRI
eCPRI core from Chip Interfaces is a highly scalable and silicon agnostic implementation of the eCPRI standard targeting any ASIC or FPGA technologies...
186
10.0
Reed Solomon Forward Error Correction Encoder Decoder
The Reed Solomon Forward Error Correction (RS FEC) IP is a highly optimized and silicon agnostic implementation of the RS FEC encoder and decoder algo...
187
10.0
JESD204D - Succesfully Taped out, Silicon Agnostic IP core
The JESD204D Controller IP is based on the recently released D revision of the JEDEC standard for Serial Interface for Data Converters. The JESD204D I...
188
10.0
MIPI I3C Controller and Target fully featured IP solution
The MIPI I3C Controller IP is a highly optimized and technology-agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both ASIC and F...
189
10.0
Interlaken Controller
Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload...
190
10.0
CPRI 6.1
Common Public Radio Interface (CPRI) 6.1 core is a silicon agnostic implementation of the CPRI 6.1 specification, which is targeting both ASIC and FPG...
191
10.0
CPRI 7.0
Chip Interfaces Common Public Radio Interface (CPRI) 7.0 core is a silicon agnostic implementation of the CPRI 7.0 specification, which is targeting b...
192
5.0
DiFi IP core
The DiFi IP core is a highly scalable and silicon agnostic implementation of the IEEE-ISTO Std 4900-2021: Digital IF Interoperability Standard v1.2.1 ...
193
5.0
MIPI CSI-2
The MIPI CSI-2 IP core is a highly scalable and silicon-agnostic implementation of the MIPI Camera Serial Interface 2 version 4.1 targeting ASIC and ...
194
5.0
MIPI RFFE Master IP Core
The MIPI RFFE Master controller IP is a highly optimized and technology agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ASIC an...
195
5.0
MIPI RFFE Slave IP Core
The MIPI RFFE Slave controller IP is a highly optimized and technology and PHY agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ...
196
5.0
ORAN
Chip Interfaces ORAN IP core is a highly scalable and silicon agnostic implementation of the interoperable O-RAN WG4 defined 7.2x interface for deploy...
197
0.118
40nm LP DDR3/4 LPDDR23 COMBO PHY DATA Block for Flip Chip usage
40nm LP DDR3/4 LPDDR23 COMBO PHY DATA Block for Flip Chip usage...
198
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process...
199
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process...
200
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...